Re: [PATCH 18/20] dt-bindings:iio:adc:amlogic,meson-saradc yaml conversion

[Jonathan Cameron <jic23@kernel.org>]

On Sun, 6 Sep 2020 12:00:02 +0200
Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:

> Hi Jonathan,
> 
> On Sat, Sep 5, 2020 at 7:32 PM Jonathan Cameron <jic23@kernel.org> wrote:
> >
> > From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> >
> > This binding is non trivial due to the range of different parts
> > supported having several subtle quirks.  
> thank you for working on this!
> 
> > I am far from sure I have these correct. For example:
> > 1) Can we have the clock adc_sel without adc_clk?  
> adc_sel and adc_clk only exist on GXBB and newer
> Meson8, Meson8b and Meson8m2 have these clocks built into the SAR ADC IP block

Ah. That makes sense.

> 
> > 2) I haven't restricted the amlogic,hhi-sysctrl to only
> >    be present on the relevant parts if nvmem stuff also is, but
> >    it would seem to be rather odd if it were otherwise.  
> yes, I think we can restrict this later
> 
> [...]
> > +        adc@9680 {
> > +            compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
> > +            #io-channel-cells = <1>;
> > +            reg = <0x0 0x9680 0x0 0x34>;
> > +            interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
> > +            clocks = <&xtal>,
> > +                <&clkc CLKID_SAR_ADC>,
> > +                <&clkc CLKID_SAR_ADC_CLK>,
> > +                <&clkc CLKID_SAR_ADC_SEL>;
> > +            clock-names = "clkin", "core";  
> CLKID_SAR_ADC_CLK and CLKID_SAR_ADC_SEL should not be in this Meson8b example
> 
> I have attached a patch for this as well as for making the clock
> selection more restrictive (to catch errors like this). feel free to
> include it in your patch if you think that it improves things

Great thanks. I'll roll your patch into this for v2.

Thanks,

Jonathan

> 
> 
> Best regards,
> Martin