From: Christoph Hellwig <hch@infradead.org>
To: Yash Shah <yash.shah@sifive.com>
Cc: robh+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com,
bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com,
devicetree@vger.kernel.org, aou@eecs.berkeley.edu,
linux-kernel@vger.kernel.org, sachin.ghadi@sifive.com,
rrichter@marvell.com, james.morse@arm.com,
linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org
Subject: Re: [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver
Date: Mon, 7 Sep 2020 07:11:26 +0100 [thread overview]
Message-ID: <20200907061126.GA14999@infradead.org> (raw)
In-Reply-To: <1599457679-8947-3-git-send-email-yash.shah@sifive.com>
On Mon, Sep 07, 2020 at 11:17:58AM +0530, Yash Shah wrote:
> Add a driver to manage the Cadence DDR controller present on SiFive SoCs
> At present the driver manages the EDAC feature of the DDR controller.
> Additional features may be added to the driver in future to control
> other aspects of the DDR controller.
So if this is a generic(ish) Cadence IP block shouldn't it be named
Cadence and made generic? Or is the frontend somehow SiFive specific?
next prev parent reply other threads:[~2020-09-07 6:11 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-07 5:47 [PATCH v2 0/3] SiFive DDR controller and EDAC support Yash Shah
2020-09-07 5:47 ` [PATCH v2 1/3] dt-bindings: riscv: Add DT documentation for DDR Controller in SiFive SoCs Yash Shah
2020-09-15 15:24 ` Rob Herring
2020-09-07 5:47 ` [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver Yash Shah
2020-09-07 5:54 ` Randy Dunlap
2020-09-07 6:11 ` Christoph Hellwig [this message]
2020-09-09 3:12 ` Palmer Dabbelt
2020-09-09 3:56 ` Yash Shah
2020-09-09 6:00 ` Christoph Hellwig
2020-09-09 20:31 ` Palmer Dabbelt
2020-09-17 9:56 ` Dhananjay Vilasrao Kangude
2020-09-07 5:47 ` [PATCH v2 3/3] EDAC/sifive: Add EDAC support for Memory Controller in SiFive SoCs Yash Shah
2020-09-23 17:10 ` Borislav Petkov
2020-09-15 15:22 ` [PATCH v2 0/3] SiFive DDR controller and EDAC support Rob Herring
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