From: Rob Herring <robh@kernel.org>
To: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linuxppc-dev@lists.ozlabs.org, bhelgaas@google.com,
lorenzo.pieralisi@arm.com, shawnguo@kernel.org,
leoyang.li@nxp.com, kishon@ti.com, gustavo.pimentel@synopsys.com,
roy.zang@nxp.com, jingoohan1@gmail.com, andrew.murray@arm.com,
mingkai.hu@nxp.com, minghuan.Lian@nxp.com,
Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: Re: [PATCHv7 02/12] PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode
Date: Thu, 10 Sep 2020 11:58:04 -0600 [thread overview]
Message-ID: <20200910175804.GA592152@bogus> (raw)
In-Reply-To: <20200811095441.7636-3-Zhiqiang.Hou@nxp.com>
On Tue, Aug 11, 2020 at 05:54:31PM +0800, Zhiqiang Hou wrote:
> From: Xiaowei Bao <xiaowei.bao@nxp.com>
>
> Add the doorbell mode of MSI-X in DWC EP driver.
>
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V7:
> - Rebase the patch without functionality change.
>
> drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++++++++++++++
> drivers/pci/controller/dwc/pcie-designware.h | 12 ++++++++++++
> 2 files changed, 26 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index e5bd3a5ef380..e76b504ed465 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -471,6 +471,20 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
> return 0;
> }
>
> +int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
return void. It never has an error.
It could also just be an inline function.
> + u16 interrupt_num)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + u32 msg_data;
> +
> + msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) |
> + (interrupt_num - 1);
> +
> + dw_pcie_writel_dbi(pci, PCIE_MSIX_DOORBELL, msg_data);
> +
> + return 0;
> +}
> +
> int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
> u16 interrupt_num)
> {
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 89f8271ec5ee..745b4938225a 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -97,6 +97,9 @@
> #define PCIE_MISC_CONTROL_1_OFF 0x8BC
> #define PCIE_DBI_RO_WR_EN BIT(0)
>
> +#define PCIE_MSIX_DOORBELL 0x948
> +#define PCIE_MSIX_DOORBELL_PF_SHIFT 24
> +
> #define PCIE_PL_CHK_REG_CONTROL_STATUS 0xB20
> #define PCIE_PL_CHK_REG_CHK_REG_START BIT(0)
> #define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1)
> @@ -434,6 +437,8 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
> u8 interrupt_num);
> int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
> u16 interrupt_num);
> +int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
> + u16 interrupt_num);
> void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
> #else
> static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
> @@ -475,6 +480,13 @@ static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
> return 0;
> }
>
> +static inline int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep,
> + u8 func_no,
> + u16 interrupt_num)
> +{
> + return 0;
> +}
> +
> static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
> {
> }
> --
> 2.17.1
>
next prev parent reply other threads:[~2020-09-10 18:44 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-11 9:54 [PATCHv7 00/12]PCI: dwc: Add the multiple PF support for DWC and Layerscape Zhiqiang Hou
2020-08-11 9:54 ` [PATCHv7 01/12] PCI: designware-ep: Add multiple PFs support for DWC Zhiqiang Hou
2020-08-11 9:54 ` [PATCHv7 02/12] PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode Zhiqiang Hou
2020-09-10 17:58 ` Rob Herring [this message]
2020-09-13 16:28 ` Z.q. Hou
2020-08-11 9:54 ` [PATCHv7 03/12] PCI: designware-ep: Move the function of getting MSI capability forward Zhiqiang Hou
2020-08-11 9:54 ` [PATCHv7 04/12] PCI: designware-ep: Modify MSI and MSIX CAP way of finding Zhiqiang Hou
2020-09-10 18:10 ` Rob Herring
2020-09-13 17:24 ` Z.q. Hou
2020-09-18 8:15 ` Z.q. Hou
2020-08-11 9:54 ` [PATCHv7 05/12] dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088a Zhiqiang Hou
2020-08-11 9:54 ` [PATCHv7 06/12] PCI: layerscape: Fix some format issue of the code Zhiqiang Hou
2020-08-11 9:54 ` [PATCHv7 07/12] PCI: layerscape: Modify the way of getting capability with different PEX Zhiqiang Hou
2020-08-11 9:54 ` [PATCHv7 08/12] PCI: layerscape: Modify the MSIX to the doorbell mode Zhiqiang Hou
2020-08-11 9:54 ` [PATCHv7 09/12] PCI: layerscape: Add EP mode support for ls1088a and ls2088a Zhiqiang Hou
2020-08-11 9:54 ` [PATCHv7 10/12] arm64: dts: layerscape: Add PCIe EP node for ls1088a Zhiqiang Hou
2020-09-10 16:47 ` Rob Herring
2020-09-13 16:26 ` Z.q. Hou
2020-08-11 9:54 ` [PATCHv7 11/12] misc: pci_endpoint_test: Add LS1088a in pci_device_id table Zhiqiang Hou
2020-08-11 9:54 ` [PATCHv7 12/12] misc: pci_endpoint_test: Add driver data for Layerscape PCIe controllers Zhiqiang Hou
2020-09-10 18:17 ` Rob Herring
2020-09-13 17:24 ` Z.q. Hou
2020-09-17 16:20 ` [PATCHv7 00/12]PCI: dwc: Add the multiple PF support for DWC and Layerscape Lorenzo Pieralisi
2020-09-18 2:55 ` Z.q. Hou
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