* [PATCH 0/3] Mediatek MT8192 scpsys support
@ 2020-09-04 6:44 Weiyi Lu
2020-09-04 6:44 ` [PATCH 1/3] dt-bindings: soc: Add MT8192 power dt-bindings Weiyi Lu
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Weiyi Lu @ 2020-09-04 6:44 UTC (permalink / raw)
To: Enric Balletbo Serra, Matthias Brugger, Nicolas Boichat,
Rob Herring, Sascha Hauer
Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek,
srv_heupstream, Weiyi Lu
This series is based on v5.9-rc1, MT8192 clock v3[1] and MT8183 scpsys v17[2].
[1] https://patchwork.kernel.org/cover/11752231/
[2] https://patchwork.kernel.org/cover/11703253/
Weiyi Lu (3):
dt-bindings: soc: Add MT8192 power dt-bindings
soc: mediatek: Add MT8192 scpsys support
arm64: dts: Add power controller device node of MT8192
.../bindings/soc/mediatek/scpsys.txt | 5 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 148 +++++++++
drivers/soc/mediatek/mtk-scpsys.c | 297 ++++++++++++++++++
include/dt-bindings/power/mt8192-power.h | 32 ++
4 files changed, 482 insertions(+)
create mode 100644 include/dt-bindings/power/mt8192-power.h
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 1/3] dt-bindings: soc: Add MT8192 power dt-bindings 2020-09-04 6:44 [PATCH 0/3] Mediatek MT8192 scpsys support Weiyi Lu @ 2020-09-04 6:44 ` Weiyi Lu 2020-09-14 21:06 ` Rob Herring 2020-09-04 6:44 ` [PATCH 2/3] soc: mediatek: Add MT8192 scpsys support Weiyi Lu ` (2 subsequent siblings) 3 siblings, 1 reply; 6+ messages in thread From: Weiyi Lu @ 2020-09-04 6:44 UTC (permalink / raw) To: Enric Balletbo Serra, Matthias Brugger, Nicolas Boichat, Rob Herring, Sascha Hauer Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek, srv_heupstream, Weiyi Lu Add power dt-bindings of MT8192 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> --- .../devicetree/bindings/soc/mediatek/scpsys.txt | 5 ++++ include/dt-bindings/power/mt8192-power.h | 32 ++++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 include/dt-bindings/power/mt8192-power.h diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt index efe2025..7f322f9 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt @@ -16,6 +16,7 @@ power/power-domain.yaml. It provides the power domains defined in - include/dt-bindings/power/mt2712-power.h - include/dt-bindings/power/mt7622-power.h - include/dt-bindings/power/mt8183-power.h +- include/dt-bindings/power/mt8192-power.h Required properties for power controller: - compatible: Should be one of: @@ -29,6 +30,7 @@ Required properties for power controller: - "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC - "mediatek,mt8173-scpsys" - "mediatek,mt8183-scpsys" + - "mediatek,mt8192-scpsys" - #power-domain-cells: Must be 1 - #address-cells: Should be 1 - #size-cells: Should be 0 @@ -50,6 +52,9 @@ Required properties for power controller: Required clocks for MT8183: "audio", "audio1", "audio2", "mfg", "mm", "cam", "isp", "vpu", "vpu1", "vpu2", "vpu3"; + Required clocks for MT8192: "audio", "audio1", "audio2", "conn", "mfg", + "disp", "disp1", "ipe", "isp", "isp1", + "mdp", "venc", "vdec", "cam" Optional properties for power controller: - vdec-supply: Power supply for the vdec power domain diff --git a/include/dt-bindings/power/mt8192-power.h b/include/dt-bindings/power/mt8192-power.h new file mode 100644 index 0000000..4eaa53d --- /dev/null +++ b/include/dt-bindings/power/mt8192-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2020 MediaTek Inc. + * Author: Weiyi Lu <weiyi.lu@mediatek.com> + */ + +#ifndef _DT_BINDINGS_POWER_MT8192_POWER_H +#define _DT_BINDINGS_POWER_MT8192_POWER_H + +#define MT8192_POWER_DOMAIN_AUDIO 0 +#define MT8192_POWER_DOMAIN_CONN 1 +#define MT8192_POWER_DOMAIN_MFG0 2 +#define MT8192_POWER_DOMAIN_MFG1 3 +#define MT8192_POWER_DOMAIN_MFG2 4 +#define MT8192_POWER_DOMAIN_MFG3 5 +#define MT8192_POWER_DOMAIN_MFG4 6 +#define MT8192_POWER_DOMAIN_MFG5 7 +#define MT8192_POWER_DOMAIN_MFG6 8 +#define MT8192_POWER_DOMAIN_DISP 9 +#define MT8192_POWER_DOMAIN_IPE 10 +#define MT8192_POWER_DOMAIN_ISP 11 +#define MT8192_POWER_DOMAIN_ISP2 12 +#define MT8192_POWER_DOMAIN_MDP 13 +#define MT8192_POWER_DOMAIN_VENC 14 +#define MT8192_POWER_DOMAIN_VDEC 15 +#define MT8192_POWER_DOMAIN_VDEC2 16 +#define MT8192_POWER_DOMAIN_CAM 17 +#define MT8192_POWER_DOMAIN_CAM_RAWA 18 +#define MT8192_POWER_DOMAIN_CAM_RAWB 19 +#define MT8192_POWER_DOMAIN_CAM_RAWC 20 + +#endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */ -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] dt-bindings: soc: Add MT8192 power dt-bindings 2020-09-04 6:44 ` [PATCH 1/3] dt-bindings: soc: Add MT8192 power dt-bindings Weiyi Lu @ 2020-09-14 21:06 ` Rob Herring 0 siblings, 0 replies; 6+ messages in thread From: Rob Herring @ 2020-09-14 21:06 UTC (permalink / raw) To: Weiyi Lu Cc: linux-mediatek, linux-kernel, Enric Balletbo Serra, Matthias Brugger, srv_heupstream, Sascha Hauer, devicetree, linux-arm-kernel, Nicolas Boichat On Fri, 04 Sep 2020 14:44:53 +0800, Weiyi Lu wrote: > Add power dt-bindings of MT8192 > > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> > --- > .../devicetree/bindings/soc/mediatek/scpsys.txt | 5 ++++ > include/dt-bindings/power/mt8192-power.h | 32 ++++++++++++++++++++++ > 2 files changed, 37 insertions(+) > create mode 100644 include/dt-bindings/power/mt8192-power.h > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/3] soc: mediatek: Add MT8192 scpsys support 2020-09-04 6:44 [PATCH 0/3] Mediatek MT8192 scpsys support Weiyi Lu 2020-09-04 6:44 ` [PATCH 1/3] dt-bindings: soc: Add MT8192 power dt-bindings Weiyi Lu @ 2020-09-04 6:44 ` Weiyi Lu 2020-09-04 6:44 ` [PATCH 3/3] arm64: dts: Add power controller device node of MT8192 Weiyi Lu 2020-09-15 9:34 ` [PATCH 0/3] Mediatek MT8192 scpsys support Matthias Brugger 3 siblings, 0 replies; 6+ messages in thread From: Weiyi Lu @ 2020-09-04 6:44 UTC (permalink / raw) To: Enric Balletbo Serra, Matthias Brugger, Nicolas Boichat, Rob Herring, Sascha Hauer Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek, srv_heupstream, Weiyi Lu Add scpsys driver for MT8192 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> --- drivers/soc/mediatek/mtk-scpsys.c | 297 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 297 insertions(+) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index 7158863b..19a0c7e 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -21,6 +21,7 @@ #include <dt-bindings/power/mt7623a-power.h> #include <dt-bindings/power/mt8173-power.h> #include <dt-bindings/power/mt8183-power.h> +#include <dt-bindings/power/mt8192-power.h> #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -129,6 +130,43 @@ #define MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP (BIT(5) | BIT(6)) #define MT8183_SMI_COMMON_SMI_CLAMP_VDEC BIT(7) +#define MT8192_TOP_AXI_PROT_EN_DISP (BIT(6) | BIT(23)) +#define MT8192_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(18)) +#define MT8192_TOP_AXI_PROT_EN_CONN_2ND BIT(14) +#define MT8192_TOP_AXI_PROT_EN_MFG1 GENMASK(22, 21) +#define MT8192_TOP_AXI_PROT_EN_1_CONN BIT(10) +#define MT8192_TOP_AXI_PROT_EN_1_MFG1 BIT(21) +#define MT8192_TOP_AXI_PROT_EN_1_CAM BIT(22) +#define MT8192_TOP_AXI_PROT_EN_2_CAM BIT(0) +#define MT8192_TOP_AXI_PROT_EN_2_ADSP BIT(3) +#define MT8192_TOP_AXI_PROT_EN_2_AUDIO BIT(4) +#define MT8192_TOP_AXI_PROT_EN_2_MFG1 GENMASK(6, 5) +#define MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND BIT(7) +#define MT8192_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2)) +#define MT8192_TOP_AXI_PROT_EN_MM_DISP (BIT(0) | BIT(2) | \ + BIT(10) | BIT(12) | \ + BIT(14) | BIT(16) | \ + BIT(24) | BIT(26)) +#define MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND (BIT(1) | BIT(3)) +#define MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND (BIT(1) | BIT(3) | \ + BIT(15) | BIT(17) | \ + BIT(25) | BIT(27)) +#define MT8192_TOP_AXI_PROT_EN_MM_ISP2 BIT(14) +#define MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND BIT(15) +#define MT8192_TOP_AXI_PROT_EN_MM_IPE BIT(16) +#define MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND BIT(17) +#define MT8192_TOP_AXI_PROT_EN_MM_VDEC BIT(24) +#define MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND BIT(25) +#define MT8192_TOP_AXI_PROT_EN_MM_VENC BIT(26) +#define MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(27) +#define MT8192_TOP_AXI_PROT_EN_MM_2_ISP BIT(8) +#define MT8192_TOP_AXI_PROT_EN_MM_2_DISP (BIT(8) | BIT(12)) +#define MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND BIT(9) +#define MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND (BIT(9) | BIT(13)) +#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP BIT(12) +#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13) +#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21) + #define MAX_CLKS 3 #define MAX_SUBSYS_CLKS 10 @@ -1463,6 +1501,253 @@ static void mtk_register_power_domains(struct platform_device *pdev, }, }; +/* + * MT8192 power domain support + */ + +static const struct scp_domain_data scp_domain_data_mt8192[] = { + [MT8192_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = BIT(21), + .ctl_offs = 0x0354, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_name = {"audio", "audio1", "audio2"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x714, 0x718, 0x710, 0x724, + MT8192_TOP_AXI_PROT_EN_2_AUDIO), + }, + }, + [MT8192_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = 0x0304, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .basic_clk_name = {"conn"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0x220, 0x228, + MT8192_TOP_AXI_PROT_EN_CONN), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0x220, 0x228, + MT8192_TOP_AXI_PROT_EN_CONN_2ND), + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0x250, 0x258, + MT8192_TOP_AXI_PROT_EN_1_CONN), + }, + }, + [MT8192_POWER_DOMAIN_MFG0] = { + .name = "mfg", + .sta_mask = BIT(2), + .ctl_offs = 0x0308, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_name = {"mfg"}, + }, + [MT8192_POWER_DOMAIN_MFG1] = { + .name = "mfg1", + .sta_mask = BIT(3), + .ctl_offs = 0x030c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0x250, 0x258, + MT8192_TOP_AXI_PROT_EN_1_MFG1), + BUS_PROT(IFR_TYPE, 0x714, 0x718, 0x710, 0x724, + MT8192_TOP_AXI_PROT_EN_2_MFG1), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0x220, 0x228, + MT8192_TOP_AXI_PROT_EN_MFG1), + BUS_PROT(IFR_TYPE, 0x714, 0x718, 0x710, 0x724, + MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND), + }, + }, + [MT8192_POWER_DOMAIN_MFG2] = { + .name = "mfg2", + .sta_mask = BIT(4), + .ctl_offs = 0x0310, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_MFG3] = { + .name = "mfg3", + .sta_mask = BIT(5), + .ctl_offs = 0x0314, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_MFG4] = { + .name = "mfg4", + .sta_mask = BIT(6), + .ctl_offs = 0x0318, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_MFG5] = { + .name = "mfg5", + .sta_mask = BIT(7), + .ctl_offs = 0x031c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_MFG6] = { + .name = "mfg6", + .sta_mask = BIT(8), + .ctl_offs = 0x0320, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_DISP] = { + .name = "disp", + .sta_mask = BIT(20), + .ctl_offs = 0x0350, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_name = {"disp", "disp1"}, + .bp_table = { + BUS_PROT_IGN(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, + MT8192_TOP_AXI_PROT_EN_MM_DISP), + BUS_PROT_IGN(IFR_TYPE, 0xdcc, 0xdd0, 0xdc8, 0xdd8, + MT8192_TOP_AXI_PROT_EN_MM_2_DISP), + BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0x220, 0x228, + MT8192_TOP_AXI_PROT_EN_DISP), + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, + MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND), + BUS_PROT(IFR_TYPE, 0xdcc, 0xdd0, 0xdc8, 0xdd8, + MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND), + }, + }, + [MT8192_POWER_DOMAIN_IPE] = { + .name = "ipe", + .sta_mask = BIT(14), + .ctl_offs = 0x0338, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_name = {"ipe"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, + MT8192_TOP_AXI_PROT_EN_MM_IPE), + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, + MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND), + }, + }, + [MT8192_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = BIT(12), + .ctl_offs = 0x0330, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_name = {"isp"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0xdcc, 0xdd0, 0xdc8, 0xdd8, + MT8192_TOP_AXI_PROT_EN_MM_2_ISP), + BUS_PROT(IFR_TYPE, 0xdcc, 0xdd0, 0xdc8, 0xdd8, + MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND), + }, + }, + [MT8192_POWER_DOMAIN_ISP2] = { + .name = "isp2", + .sta_mask = BIT(13), + .ctl_offs = 0x0334, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_name = {"isp1"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, + MT8192_TOP_AXI_PROT_EN_MM_ISP2), + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, + MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND), + }, + }, + [MT8192_POWER_DOMAIN_MDP] = { + .name = "mdp", + .sta_mask = BIT(19), + .ctl_offs = 0x034c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_name = {"mdp"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0xdcc, 0xdd0, 0xdc8, 0xdd8, + MT8192_TOP_AXI_PROT_EN_MM_2_MDP), + BUS_PROT(IFR_TYPE, 0xdcc, 0xdd0, 0xdc8, 0xdd8, + MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND), + }, + }, + [MT8192_POWER_DOMAIN_VENC] = { + .name = "venc", + .sta_mask = BIT(17), + .ctl_offs = 0x0344, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_name = {"venc"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, + MT8192_TOP_AXI_PROT_EN_MM_VENC), + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, + MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND), + }, + }, + [MT8192_POWER_DOMAIN_VDEC] = { + .name = "vdec", + .sta_mask = BIT(15), + .ctl_offs = 0x033c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_name = {"vdec"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, + MT8192_TOP_AXI_PROT_EN_MM_VDEC), + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, + MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND), + }, + }, + [MT8192_POWER_DOMAIN_VDEC2] = { + .name = "vdec2", + .sta_mask = BIT(16), + .ctl_offs = 0x0340, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(23), + .ctl_offs = 0x035c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .basic_clk_name = {"cam"}, + .bp_table = { + BUS_PROT(IFR_TYPE, 0x714, 0x718, 0x710, 0x724, + MT8192_TOP_AXI_PROT_EN_2_CAM), + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, + MT8192_TOP_AXI_PROT_EN_MM_CAM), + BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0x250, 0x258, + MT8192_TOP_AXI_PROT_EN_1_CAM), + BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0x2d0, 0x2ec, + MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND), + BUS_PROT(IFR_TYPE, 0xb84, 0xb88, 0xb80, 0xb90, + MT8192_TOP_AXI_PROT_EN_VDNR_CAM), + }, + }, + [MT8192_POWER_DOMAIN_CAM_RAWA] = { + .name = "cam_rawa", + .sta_mask = BIT(24), + .ctl_offs = 0x0360, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_CAM_RAWB] = { + .name = "cam_rawb", + .sta_mask = BIT(25), + .ctl_offs = 0x0364, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_CAM_RAWC] = { + .name = "cam_rawc", + .sta_mask = BIT(26), + .ctl_offs = 0x0368, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, +}; + static const struct scp_soc_data mt2701_data = { .domains = scp_domain_data_mt2701, .num_domains = ARRAY_SIZE(scp_domain_data_mt2701), @@ -1532,6 +1817,15 @@ static void mtk_register_power_domains(struct platform_device *pdev, } }; +static const struct scp_soc_data mt8192_data = { + .domains = scp_domain_data_mt8192, + .num_domains = ARRAY_SIZE(scp_domain_data_mt8192), + .regs = { + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, + }, +}; + /* * scpsys driver init */ @@ -1559,6 +1853,9 @@ static void mtk_register_power_domains(struct platform_device *pdev, .compatible = "mediatek,mt8183-scpsys", .data = &mt8183_data, }, { + .compatible = "mediatek,mt8192-scpsys", + .data = &mt8192_data, + }, { /* sentinel */ } }; -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/3] arm64: dts: Add power controller device node of MT8192 2020-09-04 6:44 [PATCH 0/3] Mediatek MT8192 scpsys support Weiyi Lu 2020-09-04 6:44 ` [PATCH 1/3] dt-bindings: soc: Add MT8192 power dt-bindings Weiyi Lu 2020-09-04 6:44 ` [PATCH 2/3] soc: mediatek: Add MT8192 scpsys support Weiyi Lu @ 2020-09-04 6:44 ` Weiyi Lu 2020-09-15 9:34 ` [PATCH 0/3] Mediatek MT8192 scpsys support Matthias Brugger 3 siblings, 0 replies; 6+ messages in thread From: Weiyi Lu @ 2020-09-04 6:44 UTC (permalink / raw) To: Enric Balletbo Serra, Matthias Brugger, Nicolas Boichat, Rob Herring, Sascha Hauer Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek, srv_heupstream, Weiyi Lu Add power controller node for MT8192. In scpsys node, it contains clocks and regmapping of infracfg for bus protection. And list all the power domains of MT8192 under scpsys node to show the dependency between each other through hierarchical structure. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 148 +++++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index b3fab4f..be90137 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/mt8192-pinfunc.h> +#include <dt-bindings/power/mt8192-power.h> / { compatible = "mediatek,mt8192"; @@ -257,6 +258,153 @@ #interrupt-cells = <2>; }; + scpsys: power-controller@10006000 { + compatible = "mediatek,mt8192-scpsys", "syscon"; + reg = <0 0x10006000 0 0x1000>; + clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&infracfg CLK_INFRA_AUDIO_26M_B>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_PMIC_CONN>, + <&topckgen CLK_TOP_MFG_PLL_SEL>, + <&topckgen CLK_TOP_DISP_SEL>, + <&infracfg CLK_INFRA_DEVICE_APC_SYNC>, + <&topckgen CLK_TOP_IPE_SEL>, + <&topckgen CLK_TOP_IMG1_SEL>, + <&topckgen CLK_TOP_IMG2_SEL>, + <&topckgen CLK_TOP_MDP_SEL>, + <&topckgen CLK_TOP_VENC_SEL>, + <&topckgen CLK_TOP_VDEC_SEL>, + <&topckgen CLK_TOP_CAM_SEL>; + clock-names = "audio", "audio1", "audio2", "conn", "mfg", + "disp", "disp1", "ipe", "isp", "isp1", + "mdp", "venc", "vdec", "cam"; + infracfg = <&infracfg>; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + audio@MT8192_POWER_DOMAIN_AUDIO { + reg = <MT8192_POWER_DOMAIN_AUDIO>; + }; + + conn@MT8192_POWER_DOMAIN_CONN { + reg = <MT8192_POWER_DOMAIN_CONN>; + }; + + mfg@MT8192_POWER_DOMAIN_MFG0 { + reg = <MT8192_POWER_DOMAIN_MFG0>; + #address-cells = <1>; + #size-cells = <0>; + + mfg1@MT8192_POWER_DOMAIN_MFG1 { + reg = <MT8192_POWER_DOMAIN_MFG1>; + #address-cells = <1>; + #size-cells = <0>; + + mfg2@MT8192_POWER_DOMAIN_MFG2 { + reg = <MT8192_POWER_DOMAIN_MFG2>; + }; + + mfg3@MT8192_POWER_DOMAIN_MFG3 { + reg = <MT8192_POWER_DOMAIN_MFG3>; + }; + + mfg4@MT8192_POWER_DOMAIN_MFG4 { + reg = <MT8192_POWER_DOMAIN_MFG4>; + }; + + mfg5@MT8192_POWER_DOMAIN_MFG5 { + reg = <MT8192_POWER_DOMAIN_MFG5>; + }; + + mfg6@MT8192_POWER_DOMAIN_MFG6 { + reg = <MT8192_POWER_DOMAIN_MFG6>; + }; + }; + }; + + disp@MT8192_POWER_DOMAIN_DISP { + reg = <MT8192_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_IOMMU>; + #address-cells = <1>; + #size-cells = <0>; + + ipe@MT8192_POWER_DOMAIN_IPE { + reg = <MT8192_POWER_DOMAIN_IPE>; + clocks = <&ipesys CLK_IPE_LARB19>, + <&ipesys CLK_IPE_LARB20>, + <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_GALS>; + }; + + isp@MT8192_POWER_DOMAIN_ISP { + reg = <MT8192_POWER_DOMAIN_ISP>; + clocks = <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + }; + + isp2@MT8192_POWER_DOMAIN_ISP2 { + reg = <MT8192_POWER_DOMAIN_ISP2>; + clocks = <&imgsys2 CLK_IMG2_LARB11>, + <&imgsys2 CLK_IMG2_GALS>; + }; + + mdp@MT8192_POWER_DOMAIN_MDP { + reg = <MT8192_POWER_DOMAIN_MDP>; + clocks = <&mdpsys CLK_MDP_SMI0>; + }; + + venc@MT8192_POWER_DOMAIN_VENC { + reg = <MT8192_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_SET1_VENC>; + }; + + vdec@MT8192_POWER_DOMAIN_VDEC { + reg = <MT8192_POWER_DOMAIN_VDEC>; + clocks = <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + #address-cells = <1>; + #size-cells = <0>; + + vdec2@MT8192_POWER_DOMAIN_VDEC2 { + reg = <MT8192_POWER_DOMAIN_VDEC2>; + clocks = <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>; + }; + }; + + cam@MT8192_POWER_DOMAIN_CAM { + reg = <MT8192_POWER_DOMAIN_CAM>; + clocks = <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_CCU_GALS>, + <&camsys CLK_CAM_CAM2MM_GALS>; + #address-cells = <1>; + #size-cells = <0>; + + cam_rawa@MT8192_POWER_DOMAIN_CAM_RAWA { + reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; + clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; + }; + + cam_rawb@MT8192_POWER_DOMAIN_CAM_RAWB { + reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; + clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; + }; + + cam_rawc@MT8192_POWER_DOMAIN_CAM_RAWC { + reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; + clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; + }; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8192-wdt"; reg = <0 0x10007000 0 0x100>; -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 0/3] Mediatek MT8192 scpsys support 2020-09-04 6:44 [PATCH 0/3] Mediatek MT8192 scpsys support Weiyi Lu ` (2 preceding siblings ...) 2020-09-04 6:44 ` [PATCH 3/3] arm64: dts: Add power controller device node of MT8192 Weiyi Lu @ 2020-09-15 9:34 ` Matthias Brugger 3 siblings, 0 replies; 6+ messages in thread From: Matthias Brugger @ 2020-09-15 9:34 UTC (permalink / raw) To: Weiyi Lu, Enric Balletbo Serra, Nicolas Boichat, Rob Herring, Sascha Hauer Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek, srv_heupstream Hi Weiyi, On 04/09/2020 08:44, Weiyi Lu wrote: > This series is based on v5.9-rc1, MT8192 clock v3[1] and MT8183 scpsys v17[2]. First of all, thanks for your patch! The actual scpsys driver has some limitations. Enric and I are working on a new driver [1]. My idea is to deprecate the old scpsys driver in favor of this new one. Would you mind to resend your series on top of [1]? Regards, Matthias > > [1] https://patchwork.kernel.org/cover/11752231/ > [2] https://patchwork.kernel.org/cover/11703253/ > > > Weiyi Lu (3): > dt-bindings: soc: Add MT8192 power dt-bindings > soc: mediatek: Add MT8192 scpsys support > arm64: dts: Add power controller device node of MT8192 > > .../bindings/soc/mediatek/scpsys.txt | 5 + > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 148 +++++++++ > drivers/soc/mediatek/mtk-scpsys.c | 297 ++++++++++++++++++ > include/dt-bindings/power/mt8192-power.h | 32 ++ > 4 files changed, 482 insertions(+) > create mode 100644 include/dt-bindings/power/mt8192-power.h > ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-09-15 9:34 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-09-04 6:44 [PATCH 0/3] Mediatek MT8192 scpsys support Weiyi Lu 2020-09-04 6:44 ` [PATCH 1/3] dt-bindings: soc: Add MT8192 power dt-bindings Weiyi Lu 2020-09-14 21:06 ` Rob Herring 2020-09-04 6:44 ` [PATCH 2/3] soc: mediatek: Add MT8192 scpsys support Weiyi Lu 2020-09-04 6:44 ` [PATCH 3/3] arm64: dts: Add power controller device node of MT8192 Weiyi Lu 2020-09-15 9:34 ` [PATCH 0/3] Mediatek MT8192 scpsys support Matthias Brugger
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