From: Rob Herring <robh@kernel.org>
To: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, bhelgaas@google.com,
shawnguo@kernel.org, leoyang.li@nxp.com,
lorenzo.pieralisi@arm.com, gustavo.pimentel@synopsys.com,
minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com
Subject: Re: [PATCH 2/7] PCI: layerscape: Change to use the DWC common link-up check function
Date: Mon, 14 Sep 2020 19:19:44 -0600 [thread overview]
Message-ID: <20200915011944.GB640859@bogus> (raw)
In-Reply-To: <20200907053801.22149-3-Zhiqiang.Hou@nxp.com>
On Mon, Sep 07, 2020 at 01:37:56PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
>
> The current Layerscape PCIe driver directly uses the physical layer
> LTSSM code to check the link-up state, which treats the > L0 states
> as link-up. This is not correct, since there is not explicit map
> between link-up state and LTSSM. So this patch changes to use the
> DWC common link-up check function.
>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> drivers/pci/controller/dwc/pci-layerscape.c | 141 ++------------------
> 1 file changed, 10 insertions(+), 131 deletions(-)
IIRC, the common function uses a debug register. I've been wondering do
the common PCIe config space registers not work on DWC? If you have an
answer, that would be great for some potential additional cleanups.
Either way,
Reviewed-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2020-09-15 1:19 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-07 5:37 [PATCH 0/7] PCI: layerscape: Add power management support Zhiqiang Hou
2020-09-07 5:37 ` [PATCH 1/7] PCI: dwc: Fix a bug of the case dw_pci->ops is NULL Zhiqiang Hou
2020-09-09 9:28 ` Gustavo Pimentel
2020-09-13 16:17 ` Z.q. Hou
2020-09-15 1:16 ` Rob Herring
2020-09-15 3:39 ` Z.q. Hou
2020-09-07 5:37 ` [PATCH 2/7] PCI: layerscape: Change to use the DWC common link-up check function Zhiqiang Hou
2020-09-15 1:19 ` Rob Herring [this message]
2020-09-15 6:22 ` Z.q. Hou
2020-09-07 5:37 ` [PATCH 3/7] dt-bindings: pci: layerscape-pci: Add a optional property big-endian Zhiqiang Hou
2020-09-15 1:30 ` Rob Herring
2020-09-15 3:39 ` Z.q. Hou
2020-09-07 5:37 ` [PATCH 4/7] arm64: dts: layerscape: Add big-endian property for PCIe nodes Zhiqiang Hou
2020-09-07 5:37 ` [PATCH 5/7] dt-bindings: pci: layerscape-pci: Update the description of SCFG property Zhiqiang Hou
2020-09-15 1:31 ` Rob Herring
2020-09-15 3:39 ` Z.q. Hou
2020-09-07 5:38 ` [PATCH 6/7] dts: arm64: ls1043a: Add SCFG phandle for PCIe nodes Zhiqiang Hou
2020-09-21 13:16 ` Shawn Guo
2020-09-21 16:46 ` Z.q. Hou
2020-09-07 5:38 ` [PATCH 7/7] PCI: layerscape: Add power management support Zhiqiang Hou
2020-09-15 1:30 ` Rob Herring
2020-09-15 6:44 ` Z.q. Hou
2021-03-23 11:15 ` [PATCH 0/7] " Lorenzo Pieralisi
2021-03-24 4:10 ` Z.q. Hou
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