From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E463C43461 for ; Tue, 15 Sep 2020 11:35:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E7ADA20872 for ; Tue, 15 Sep 2020 11:35:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="NjEq9dOt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726161AbgIOLfH (ORCPT ); Tue, 15 Sep 2020 07:35:07 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:45006 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726369AbgIOLey (ORCPT ); Tue, 15 Sep 2020 07:34:54 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 08FBKjGH013435; Tue, 15 Sep 2020 06:20:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1600168845; bh=HB6Ek5pzLz8fCLHNM5RI59gb394ysYTfKY+ZodmGEYk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NjEq9dOtiiNZC2rwCtkYSrFW72bqENq+eG2NT2sJqQhJ92mdkO4oadZfwn33KD5Fm BPERA85F1BjNGDURbGFiy15yeQTq/+MXgQhwo+Pn+YWpVCvrkjWnXREsilKIYHHF+0 RIpPMmMJwmLm1wPEHVdbY56aMTSJyigAuWKQi0rM= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08FBKj1h120680; Tue, 15 Sep 2020 06:20:45 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Tue, 15 Sep 2020 06:20:45 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Tue, 15 Sep 2020 06:20:45 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 08FBKdmA013285; Tue, 15 Sep 2020 06:20:42 -0500 From: Roger Quadros To: , CC: , , , , , , Roger Quadros , Peter Rosin Subject: [PATCH v3 1/6] dt-bindings: mux-j7200-wiz: Add lane function defines Date: Tue, 15 Sep 2020 14:20:33 +0300 Message-ID: <20200915112038.30219-2-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200915112038.30219-1-rogerq@ti.com> References: <20200915112038.30219-1-rogerq@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Each SERDES lane mux can select upto 4 different IPs. There are 4 lanes in each J7200 SERDES. Define all the possible functions in this file. Cc: Peter Rosin Signed-off-by: Roger Quadros --- include/dt-bindings/mux/mux-j7200-wiz.h | 29 +++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 include/dt-bindings/mux/mux-j7200-wiz.h diff --git a/include/dt-bindings/mux/mux-j7200-wiz.h b/include/dt-bindings/mux/mux-j7200-wiz.h new file mode 100644 index 000000000000..b091b1185a36 --- /dev/null +++ b/include/dt-bindings/mux/mux-j7200-wiz.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for J7200 WIZ. + */ + +#ifndef _DT_BINDINGS_J7200_WIZ +#define _DT_BINDINGS_J7200_WIZ + +#define SERDES0_LANE0_QSGMII_LANE3 0x0 +#define SERDES0_LANE0_PCIE1_LANE0 0x1 +#define SERDES0_LANE0_IP3_UNUSED 0x2 +#define SERDES0_LANE0_IP4_UNUSED 0x3 + +#define SERDES0_LANE1_QSGMII_LANE4 0x0 +#define SERDES0_LANE1_PCIE1_LANE1 0x1 +#define SERDES0_LANE1_IP3_UNUSED 0x2 +#define SERDES0_LANE1_IP4_UNUSED 0x3 + +#define SERDES0_LANE2_QSGMII_LANE1 0x0 +#define SERDES0_LANE2_PCIE1_LANE2 0x1 +#define SERDES0_LANE2_IP3_UNUSED 0x2 +#define SERDES0_LANE2_IP4_UNUSED 0x3 + +#define SERDES0_LANE3_QSGMII_LANE2 0x0 +#define SERDES0_LANE3_PCIE1_LANE3 0x1 +#define SERDES0_LANE3_USB 0x2 +#define SERDES0_LANE3_IP4_UNUSED 0x3 + +#endif /* _DT_BINDINGS_J7200_WIZ */ -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki