From: Qiang Zhao <qiang.zhao@nxp.com>
To: shawnguo@kernel.org, robh+dt@kernel.org, mturquette@baylibre.com
Cc: andy.tang@nxp.com, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
Zhao Qiang <qiang.zhao@nxp.com>
Subject: [PATCH 1/2] clk: qoriq: modify MAX_PLL_DIV to 32
Date: Wed, 16 Sep 2020 11:03:10 +0800 [thread overview]
Message-ID: <20200916030311.17280-1-qiang.zhao@nxp.com> (raw)
From: Zhao Qiang <qiang.zhao@nxp.com>
On LS2088A, Watchdog need clk divided by 32,
so modify MAX_PLL_DIV to 32
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
drivers/clk/clk-qoriq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 5942e98..46101c6 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -31,7 +31,7 @@
#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
#define CGB_PLL1 4
#define CGB_PLL2 5
-#define MAX_PLL_DIV 16
+#define MAX_PLL_DIV 32
struct clockgen_pll_div {
struct clk *clk;
--
2.7.4
next reply other threads:[~2020-09-16 3:49 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-16 3:03 Qiang Zhao [this message]
2020-09-16 3:03 ` [PATCH 2/2] arm64: dts: layerscape: modify clocks divider to 32 for wdt Qiang Zhao
2020-10-14 2:48 ` [PATCH 1/2] clk: qoriq: modify MAX_PLL_DIV to 32 Stephen Boyd
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