From: Qiang Zhao <qiang.zhao@nxp.com>
To: shawnguo@kernel.org, robh+dt@kernel.org, mturquette@baylibre.com
Cc: andy.tang@nxp.com, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
Zhao Qiang <qiang.zhao@nxp.com>
Subject: [PATCH 2/2] arm64: dts: layerscape: modify clocks divider to 32 for wdt
Date: Wed, 16 Sep 2020 11:03:11 +0800 [thread overview]
Message-ID: <20200916030311.17280-2-qiang.zhao@nxp.com> (raw)
In-Reply-To: <20200916030311.17280-1-qiang.zhao@nxp.com>
From: Zhao Qiang <qiang.zhao@nxp.com>
On LX2088A, wdt's clock are get from clockgen divided by 32,
so modify clocks in device tree.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 7016791..de6c751 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -194,56 +194,56 @@
cluster1_core0_watchdog: wdt@c000000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster1_core1_watchdog: wdt@c010000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core0_watchdog: wdt@c100000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc100000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster2_core1_watchdog: wdt@c110000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc110000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster3_core0_watchdog: wdt@c200000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc200000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster3_core1_watchdog: wdt@c210000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc210000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster4_core0_watchdog: wdt@c300000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc300000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
cluster4_core1_watchdog: wdt@c310000 {
compatible = "arm,sp805-wdt", "arm,primecell";
reg = <0x0 0xc310000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clocks = <&clockgen 4 31>, <&clockgen 4 31>;
clock-names = "apb_pclk", "wdog_clk";
};
--
2.7.4
next prev parent reply other threads:[~2020-09-16 3:49 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-16 3:03 [PATCH 1/2] clk: qoriq: modify MAX_PLL_DIV to 32 Qiang Zhao
2020-09-16 3:03 ` Qiang Zhao [this message]
2020-10-14 2:48 ` Stephen Boyd
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