[PATCH 4/5] pci: controller: dwc: qcom: Add PCIe support for SM8250 SoC

Manivannan Sadhasivam
2020-09-16T20:52:40Z

The PCIe IP on SM8250 SoC is similar to the one used on SDM845. Hence
the support is added reusing the 2.7.0 ops. Only difference is the need
of ATU base, which will be fetched opionally if provided by DT/ACPI.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 3aac77a295ba..ca8ad354e09d 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1370,6 +1370,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
struct pcie_port *pp;
struct dw_pcie *pci;
struct qcom_pcie *pcie;
+ void __iomem *atu_base;
int ret;

pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
@@ -1422,6 +1423,11 @@ static int qcom_pcie_probe(struct platform_device *pdev)
goto err_pm_runtime_put;
}

+ /* Get the optional ATU region if provided */
+ atu_base = devm_platform_ioremap_resource_byname(pdev, "atu");
+ if (!IS_ERR(atu_base))
+ pci->atu_base = atu_base;
+
pcie->phy = devm_phy_optional_get(dev, "pciephy");
if (IS_ERR(pcie->phy)) {
ret = PTR_ERR(pcie->phy);
@@ -1476,6 +1482,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
{ .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
{ .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
+ { .compatible = "qcom,pcie-sm8250", .data = &ops_2_7_0 },
{ }
};

--
2.17.1