From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D75FC433E2 for ; Thu, 17 Sep 2020 18:55:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DF4E82087D for ; Thu, 17 Sep 2020 18:55:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600368907; bh=Tf6j9/g6ssvG3k+ON3t83cV1K0lTh2I4Nkn5/PHO+4M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=NPmxR3Wnbq07N/IN2+G5gNGxZGvAv0y0oTt8n5s4qzlPF8ewknIv4zGpVPdIQdF9C MqgF6x8LAteVIwTXakpa6ThMnFR6BK7p27xCJbgT7T+JL/DDokRC7M1rB2r9Uw/HIr 4E3OKS3KWegtvBaGhqAiBsEpkFhk4IhVAQLd5TN8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726592AbgIQSzF (ORCPT ); Thu, 17 Sep 2020 14:55:05 -0400 Received: from mail.kernel.org ([198.145.29.99]:56652 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726456AbgIQSzF (ORCPT ); Thu, 17 Sep 2020 14:55:05 -0400 Received: from kozik-lap.mshome.net (unknown [194.230.155.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 7284A22211; Thu, 17 Sep 2020 18:54:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600368903; bh=Tf6j9/g6ssvG3k+ON3t83cV1K0lTh2I4Nkn5/PHO+4M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aHEyE9l2fhYri/8Ux0H7W2GgoHVPLOG2EkQ81mTkLbdbGiK0gkzM0JKUPWfBGlD/J RX2O57M3kZvkHu4GWi5pCBa444OP2Uy0KA/w/RuuV/VEj/VEzZPPOteKOsq5ab96fD 2iHgDdU1O3hD3SLYy1wu/nSGptsggS2v2TberEPw= From: Krzysztof Kozlowski To: Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Krzysztof Kozlowski , Adam Ford , Daniel Baluta , Anson Huang , Jacky Bai , Robin Gong , Peter Chen , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Tim Harvey Subject: [PATCH v2 2/4] arm64: dts: imx8mm: correct interrupt flags Date: Thu, 17 Sep 2020 20:54:47 +0200 Message-Id: <20200917185449.5687-2-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200917185449.5687-1-krzk@kernel.org> References: <20200917185449.5687-1-krzk@kernel.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING Correct the interrupt flags, assuming the author of the code wanted same logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW ACTIVE_HIGH => IRQ_TYPE_LEVEL_HIGH In case of level low interrupts, enable also internal pull up. It is required at least on imx8mm-evk, according to schematics. The schematics for Variscite imx8mm-var-som are not available and I was unable to get proper configuration from Variscite. Signed-off-by: Krzysztof Kozlowski --- Changes since v1: 1. Correct title. 2. Enable pull ups. --- arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 4 ++-- arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi | 6 +++++- 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 502faf6144b0..6de86a4f0ec4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -74,7 +74,7 @@ reg = <0x4b>; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; regulators { @@ -292,7 +292,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index f572b7d207f4..f305a530ff6f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -123,7 +123,7 @@ reg = <0x4b>; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; #clock-cells = <0>; @@ -392,7 +392,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 67ceda14d648..a56f602ba0a3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -134,7 +134,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_captouch>; interrupt-parent = <&gpio5>; - interrupts = <4 GPIO_ACTIVE_HIGH>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; touchscreen-size-x = <800>; touchscreen-size-y = <480>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index 9c6e91243ba0..4107fe914d08 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -137,7 +137,11 @@ reg = <0x4b>; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio2>; - interrupts = <8 GPIO_ACTIVE_LOW>; + /* + * The interrupt is not correct. It should be level low, + * however with internal pull up this causes IRQ storm. + */ + interrupts = <8 IRQ_TYPE_EDGE_RISING>; rohm,reset-snvs-powered; #clock-cells = <0>; -- 2.17.1