From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62FF0C43463 for ; Fri, 18 Sep 2020 15:20:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F1C292389F for ; Fri, 18 Sep 2020 15:20:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="G0JQIiIh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726285AbgIRPUP (ORCPT ); Fri, 18 Sep 2020 11:20:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725955AbgIRPUO (ORCPT ); Fri, 18 Sep 2020 11:20:14 -0400 Received: from mail-oi1-x242.google.com (mail-oi1-x242.google.com [IPv6:2607:f8b0:4864:20::242]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 874EDC0613CE for ; Fri, 18 Sep 2020 08:20:14 -0700 (PDT) Received: by mail-oi1-x242.google.com with SMTP id u126so7392420oif.13 for ; Fri, 18 Sep 2020 08:20:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=nJCca1Gpz/qntKkkfuhUuqPAs19Va9nMUQHb7GNjxCg=; b=G0JQIiIhW4dKr073ygInqGVY5kUDcU8THtTlLrQPIHIrlwNpPWOojEhsaxVflOlROF op5FB8vXuuCwPRKf04D2j486HVcIKrDbw8hIHvi5bY9XQ7EdeGncm2txHPe7puzA+6BI e5Kzk6rZYBabdhTK6VTqSwzW93dXXdjwSBjgg4nMP5i/04aZ3UolON6FZVlCwfdYo7je nS8ZXdGOCcdWuYQOhTLx3Fzy7Kf/21SMXSGUmIzrnsKTDZXvydeXQugMbSZWDk3aOkuo cXf1w/3YUSVHVnAI+652d4V/vbz4rMEFnK1pqeNFrVtmRAj1kwXOWKOESAR3s+vqrEKM VQpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=nJCca1Gpz/qntKkkfuhUuqPAs19Va9nMUQHb7GNjxCg=; b=tk7NGckcJzGZEP7IfNmX9BGkNmo4cxx95wx/6lpFwGOGFtfUvG6Nu6HYudsNB7IWZa NnuHOAm8k1o17oib55TKEGWG8XvNxAUtvHQYcjjPdK8kryjLebn7b6ozmDOfH0/2A0N5 eB23jRu403iEL/nMVAuEpdHOHDescM44McMvILowJb4lAbEULZISjzMlSBk+SHgXNqtB 46etWYNmFsl0kwHYWR6o89zJ2DSShQ5tv0NYSj93YjLK1MTFIZf8dbET+tAsDxns780G 9apPeEdHb/AL6GqL4xoLw8bj16voiIXLO6T27Yi02u5wawXG5BmX4g25zQfIbgUaWQBC ynaA== X-Gm-Message-State: AOAM533Paib+7fjEDxqiMVL9sk3yHWu8BPvDtnofU/24oLajyijTnZ4Q pM786C5oKtX5swpsOos9cn4Nbw== X-Google-Smtp-Source: ABdhPJwxwD0KlJLfqNq5E0fE74Vl81bSoHj+6hUtjJSAc48pb3MwGBc1WyGkrk3bQn9hMvBPv9EyCw== X-Received: by 2002:aca:5903:: with SMTP id n3mr10026260oib.159.1600442412373; Fri, 18 Sep 2020 08:20:12 -0700 (PDT) Received: from yoga ([2605:6000:e5cb:c100:7cad:6eff:fec8:37e4]) by smtp.gmail.com with ESMTPSA id l3sm3306211oom.18.2020.09.18.08.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Sep 2020 08:20:11 -0700 (PDT) Date: Fri, 18 Sep 2020 10:20:09 -0500 From: Bjorn Andersson To: Srinivasa Rao Mandadapu Cc: agross@kernel.org, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, rohitkr@codeaurora.org, srinivas.kandagatla@linaro.org, Ajit Pandey , Cheng-Yi Chiang , V Sujith Kumar Reddy Subject: Re: [PATCH v3] arm64: dts: qcom: sc7180: Add lpass cpu node for I2S driver Message-ID: <20200918152009.GQ1893@yoga> References: <1600435026-1876-1-git-send-email-srivasam@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1600435026-1876-1-git-send-email-srivasam@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri 18 Sep 08:17 CDT 2020, Srinivasa Rao Mandadapu wrote: > From: Ajit Pandey > > Add the I2S controller node to sc7180 dtsi. > Add pinmux for primary and secondary I2S. > > Signed-off-by: Ajit Pandey > Signed-off-by: Cheng-Yi Chiang > Signed-off-by: Srinivasa Rao Mandadapu > Signed-off-by: V Sujith Kumar Reddy Each s-o-b is a statement that this patch conforms to the license requirements of the Linux project. As such it describes the history of how this patch reached this point; starting with Ajit writing the patch, Cheng-Yi handling it, then you and finally Sujith. You sending the patch would indicate that you handled it last, so your certification should be last (and if Sujith handled the patch inbetween you should be listed twice). Please read https://www.kernel.org/doc/html/latest/process/submitting-patches.html?highlight=certificate#sign-your-work-the-developer-s-certificate-of-origin Regards, Bjorn > --- > Changes since v1: > -- Updated I2S pin control nodes with grouping common pin controls > -- Updated lpass_cpu node with proper control names > Changes since v2: > -- The plement of lpass_cpu node is changed > > arch/arm64/boot/dts/qcom/sc7180.dtsi | 69 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 69 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index 6678f1e..59c39cf 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -1742,6 +1742,45 @@ > }; > }; > > + sec_mi2s_active: sec-mi2s-active { > + pinmux { > + pins = "gpio49", "gpio50", "gpio51"; > + function = "mi2s_1"; > + }; > + > + pinconf { > + pins = "gpio49", "gpio50", "gpio51";; > + drive-strength = <8>; > + bias-pull-up; > + }; > + }; > + > + pri_mi2s_active: pri-mi2s-active { > + pinmux { > + pins = "gpio53", "gpio54", "gpio55", "gpio56"; > + function = "mi2s_0"; > + }; > + > + pinconf { > + pins = "gpio53", "gpio54", "gpio55", "gpio56"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + }; > + > + pri_mi2s_mclk_active: pri-mi2s-mclk-active { > + pinmux { > + pins = "gpio57"; > + function = "lpass_ext"; > + }; > + > + pinconf { > + pins = "gpio57"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + }; > + > sdc1_on: sdc1-on { > pinconf-clk { > pins = "sdc1_clk"; > @@ -3389,6 +3428,36 @@ > #power-domain-cells = <1>; > }; > > + lpass_cpu: lpass@62f00000 { > + compatible = "qcom,sc7180-lpass-cpu"; > + > + reg = <0 0x62f00000 0 0x29000>; > + reg-names = "lpass-lpaif"; > + > + iommus = <&apps_smmu 0x1020 0>; > + > + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; > + > + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, > + <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, > + <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, > + <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, > + <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, > + <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; > + > + clock-names = "pcnoc-sway-clk", "audio-core", > + "mclk0", "pcnoc-mport-clk", > + "mi2s-bit-clk0", "mi2s-bit-clk1"; > + > + > + #sound-dai-cells = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + interrupts = ; > + interrupt-names = "lpass-irq-lpaif"; > + }; > + > lpass_hm: clock-controller@63000000 { > compatible = "qcom,sc7180-lpasshm"; > reg = <0 0x63000000 0 0x28>; > -- > Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., > is a member of Code Aurora Forum, a Linux Foundation Collaborative Project. >