[PATCH v3 0/4] arm64: dts: ti: k3-j7200: add dma and mcu cpsw

[PATCH v3 0/4] arm64: dts: ti: k3-j7200: add dma and mcu cpsw

[Grygorii Strashko]

Hi All,

This series adds DT nodes for TI J7200 SoC
- Ringacc and UDMA nodes for Main and MCU NAVSS, which are compatible
  with J721E Soc, to enable DMA support
- MCU CPSW2g DT nodes to enable networking and board data

This series depends on:
 - [PATCH v4 0/5] arm64: Initial support for Texas Instrument's J7200 Platform [1]
   from: Lokesh Vutla <lokeshvutla@ti.com>

[1] https://patchwork.kernel.org/cover/11774429/

Changes in v3:
 - rebase on top of [1]
 - updated dependencies
 - added tested-by

Changes in v2:
 - fixed DT build warnings (Nishanth Menon)

v1: https://lore.kernel.org/patchwork/cover/1301067/

Grygorii Strashko (3):
  arm64: dts: ti: k3-j7200-main: add main navss cpts node
  arm64: dts: ti: k3-j7200-mcu: add mcu cpsw nuss node
  arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs

Peter Ujfalusi (1):
  arm64: dts: ti: k3-j7200: add DMA support

 .../dts/ti/k3-j7200-common-proc-board.dts     |  45 +++++++
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi     |  48 +++++++
 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 118 ++++++++++++++++++
 3 files changed, 211 insertions(+)

-- 
2.17.1

[PATCH v3 1/4] arm64: dts: ti: k3-j7200: add DMA support

[Grygorii Strashko]

From: Peter Ujfalusi <peter.ujfalusi@ti.com>

Add the intr, inta, ringacc and udmap nodes for main and mcu NAVSS.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi     | 36 +++++++++++++++
 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 44 +++++++++++++++++++
 2 files changed, 80 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 3df49577b06a..c5015df58cd4 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -93,6 +93,42 @@
 			interrupt-names = "rx_011";
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		main_ringacc: ringacc@3c000000 {
+			compatible = "ti,am654-navss-ringacc";
+			reg =	<0x0 0x3c000000 0x0 0x400000>,
+				<0x0 0x38000000 0x0 0x400000>,
+				<0x0 0x31120000 0x0 0x100>,
+				<0x0 0x33000000 0x0 0x40000>;
+			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+			ti,num-rings = <1024>;
+			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <211>;
+			msi-parent = <&main_udmass_inta>;
+		};
+
+		main_udmap: dma-controller@31150000 {
+			compatible = "ti,j721e-navss-main-udmap";
+			reg =	<0x0 0x31150000 0x0 0x100>,
+				<0x0 0x34000000 0x0 0x100000>,
+				<0x0 0x35000000 0x0 0x100000>;
+			reg-names = "gcfg", "rchanrt", "tchanrt";
+			msi-parent = <&main_udmass_inta>;
+			#dma-cells = <1>;
+
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <212>;
+			ti,ringacc = <&main_ringacc>;
+
+			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
+						<0x0f>, /* TX_HCHAN */
+						<0x10>; /* TX_UHCHAN */
+			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
+						<0x0b>, /* RX_HCHAN */
+						<0x0c>; /* RX_UHCHAN */
+			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+		};
 	};
 
 	main_pmx0: pinctrl@11c000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index ec2745e0768e..7ecdfdb46436 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -92,4 +92,48 @@
 		ti,sci-dev-id = <137>;
 		ti,interrupt-ranges = <16 960 16>;
 	};
+
+	cbass_mcu_navss: navss@28380000 {
+		compatible = "simple-mfd";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		dma-coherent;
+		dma-ranges;
+		ti,sci-dev-id = <232>;
+
+		mcu_ringacc: ringacc@2b800000 {
+			compatible = "ti,am654-navss-ringacc";
+			reg =	<0x0 0x2b800000 0x0 0x400000>,
+				<0x0 0x2b000000 0x0 0x400000>,
+				<0x0 0x28590000 0x0 0x100>,
+				<0x0 0x2a500000 0x0 0x40000>;
+			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+			ti,num-rings = <286>;
+			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <235>;
+			msi-parent = <&main_udmass_inta>;
+		};
+
+		mcu_udmap: dma-controller@285c0000 {
+			compatible = "ti,j721e-navss-mcu-udmap";
+			reg =	<0x0 0x285c0000 0x0 0x100>,
+				<0x0 0x2a800000 0x0 0x40000>,
+				<0x0 0x2aa00000 0x0 0x40000>;
+			reg-names = "gcfg", "rchanrt", "tchanrt";
+			msi-parent = <&main_udmass_inta>;
+			#dma-cells = <1>;
+
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <236>;
+			ti,ringacc = <&mcu_ringacc>;
+
+			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
+						<0x0f>; /* TX_HCHAN */
+			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
+						<0x0b>; /* RX_HCHAN */
+			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+		};
+	};
 };
-- 
2.17.1

Re: [PATCH v3 1/4] arm64: dts: ti: k3-j7200: add DMA support

[Suman Anna]

Hi Grygorii,

On 9/18/20 10:38 AM, Grygorii Strashko wrote:
> From: Peter Ujfalusi <peter.ujfalusi@ti.com>
> 
> Add the intr, inta, ringacc and udmap nodes for main and mcu NAVSS.

Need to update the changelog, intr and inta are not part of this revised series.

> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j7200-main.dtsi     | 36 +++++++++++++++
>  .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 44 +++++++++++++++++++
>  2 files changed, 80 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index 3df49577b06a..c5015df58cd4 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -93,6 +93,42 @@
>  			interrupt-names = "rx_011";
>  			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
>  		};
> +
> +		main_ringacc: ringacc@3c000000 {
> +			compatible = "ti,am654-navss-ringacc";
> +			reg =	<0x0 0x3c000000 0x0 0x400000>,
> +				<0x0 0x38000000 0x0 0x400000>,
> +				<0x0 0x31120000 0x0 0x100>,
> +				<0x0 0x33000000 0x0 0x40000>;
> +			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
> +			ti,num-rings = <1024>;
> +			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
> +			ti,sci = <&dmsc>;
> +			ti,sci-dev-id = <211>;
> +			msi-parent = <&main_udmass_inta>;
> +		};
> +
> +		main_udmap: dma-controller@31150000 {
> +			compatible = "ti,j721e-navss-main-udmap";
> +			reg =	<0x0 0x31150000 0x0 0x100>,
> +				<0x0 0x34000000 0x0 0x100000>,
> +				<0x0 0x35000000 0x0 0x100000>;
> +			reg-names = "gcfg", "rchanrt", "tchanrt";
> +			msi-parent = <&main_udmass_inta>;
> +			#dma-cells = <1>;
> +
> +			ti,sci = <&dmsc>;
> +			ti,sci-dev-id = <212>;
> +			ti,ringacc = <&main_ringacc>;
> +
> +			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
> +						<0x0f>, /* TX_HCHAN */
> +						<0x10>; /* TX_UHCHAN */
> +			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
> +						<0x0b>, /* RX_HCHAN */
> +						<0x0c>; /* RX_UHCHAN */
> +			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
> +		};
>  	};
>  
>  	main_pmx0: pinctrl@11c000 {
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> index ec2745e0768e..7ecdfdb46436 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> @@ -92,4 +92,48 @@
>  		ti,sci-dev-id = <137>;
>  		ti,interrupt-ranges = <16 960 16>;
>  	};
> +
> +	cbass_mcu_navss: navss@28380000 {
> +		compatible = "simple-mfd";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		dma-coherent;
> +		dma-ranges;
> +		ti,sci-dev-id = <232>;
> +
> +		mcu_ringacc: ringacc@2b800000 {
> +			compatible = "ti,am654-navss-ringacc";
> +			reg =	<0x0 0x2b800000 0x0 0x400000>,
> +				<0x0 0x2b000000 0x0 0x400000>,
> +				<0x0 0x28590000 0x0 0x100>,
> +				<0x0 0x2a500000 0x0 0x40000>;

Please use style consistent with existing dts nodes, not a fan of mismatched
usage. We are using 0x00 for the higher 32-bit addresses and sizes. Comment
applies to all the nodes and all patches in the series.

regards
Suman

> +			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
> +			ti,num-rings = <286>;
> +			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
> +			ti,sci = <&dmsc>;
> +			ti,sci-dev-id = <235>;
> +			msi-parent = <&main_udmass_inta>;
> +		};
> +
> +		mcu_udmap: dma-controller@285c0000 {
> +			compatible = "ti,j721e-navss-mcu-udmap";
> +			reg =	<0x0 0x285c0000 0x0 0x100>,
> +				<0x0 0x2a800000 0x0 0x40000>,
> +				<0x0 0x2aa00000 0x0 0x40000>;
> +			reg-names = "gcfg", "rchanrt", "tchanrt";
> +			msi-parent = <&main_udmass_inta>;
> +			#dma-cells = <1>;
> +
> +			ti,sci = <&dmsc>;
> +			ti,sci-dev-id = <236>;
> +			ti,ringacc = <&mcu_ringacc>;
> +
> +			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
> +						<0x0f>; /* TX_HCHAN */
> +			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
> +						<0x0b>; /* RX_HCHAN */
> +			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
> +		};
> +	};
>  };
> 

[PATCH v3 2/4] arm64: dts: ti: k3-j7200-main: add main navss cpts node

[Grygorii Strashko]

Add DT node for Main NAVSS CPTS module.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index c5015df58cd4..31bd0c5ffb8b 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -129,6 +129,18 @@
 						<0x0c>; /* RX_UHCHAN */
 			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 		};
+
+		cpts@310d0000 {
+			compatible = "ti,j721e-cpts";
+			reg = <0x0 0x310d0000 0x0 0x400>;
+			reg-names = "cpts";
+			clocks = <&k3_clks 201 1>;
+			clock-names = "cpts";
+			interrupts-extended = <&main_navss_intr 391>;
+			interrupt-names = "cpts";
+			ti,cpts-periodic-outputs = <6>;
+			ti,cpts-ext-ts-inputs = <8>;
+		};
 	};
 
 	main_pmx0: pinctrl@11c000 {
-- 
2.17.1

[PATCH v3 3/4] arm64: dts: ti: k3-j7200-mcu: add mcu cpsw nuss node

[Grygorii Strashko]

Add DT node for The TI j7200 MCU SoC Gigabit Ethernet two ports Switch
subsystem (MCU CPSW NUSS).

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 7ecdfdb46436..a994276a8b3d 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -34,6 +34,20 @@
 		};
 	};
 
+	mcu_conf: syscon@40f00000 {
+		compatible = "syscon", "simple-mfd";
+		reg = <0x0 0x40f00000 0x0 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x40f00000 0x20000>;
+
+		phy_gmii_sel: phy@4040 {
+			compatible = "ti,am654-phy-gmii-sel";
+			reg = <0x4040 0x4>;
+			#phy-cells = <1>;
+		};
+	};
+
 	chipid@43000014 {
 		compatible = "ti,am654-chipid";
 		reg = <0x00 0x43000014 0x00 0x4>;
@@ -136,4 +150,64 @@
 			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
 		};
 	};
+
+	mcu_cpsw: ethernet@46000000 {
+		compatible = "ti,j721e-cpsw-nuss";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0x0 0x46000000 0x0 0x200000>;
+		reg-names = "cpsw_nuss";
+		ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
+		dma-coherent;
+		clocks = <&k3_clks 18 21>;
+		clock-names = "fck";
+		power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
+
+		dmas = <&mcu_udmap 0xf000>,
+		       <&mcu_udmap 0xf001>,
+		       <&mcu_udmap 0xf002>,
+		       <&mcu_udmap 0xf003>,
+		       <&mcu_udmap 0xf004>,
+		       <&mcu_udmap 0xf005>,
+		       <&mcu_udmap 0xf006>,
+		       <&mcu_udmap 0xf007>,
+		       <&mcu_udmap 0x7000>;
+		dma-names = "tx0", "tx1", "tx2", "tx3",
+			    "tx4", "tx5", "tx6", "tx7",
+			    "rx";
+
+		ethernet-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			cpsw_port1: port@1 {
+				reg = <1>;
+				ti,mac-only;
+				label = "port1";
+				ti,syscon-efuse = <&mcu_conf 0x200>;
+				phys = <&phy_gmii_sel 1>;
+			};
+		};
+
+		davinci_mdio: mdio@f00 {
+			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+			reg = <0x0 0xf00 0x0 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&k3_clks 18 21>;
+			clock-names = "fck";
+			bus_freq = <1000000>;
+		};
+
+		cpts@3d000 {
+			compatible = "ti,am65-cpts";
+			reg = <0x0 0x3d000 0x0 0x400>;
+			clocks = <&k3_clks 18 2>;
+			clock-names = "cpts";
+			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "cpts";
+			ti,cpts-ext-ts-inputs = <4>;
+			ti,cpts-periodic-outputs = <2>;
+		};
+	};
 };
-- 
2.17.1

Re: [PATCH v3 3/4] arm64: dts: ti: k3-j7200-mcu: add mcu cpsw nuss node

[Suman Anna]

On 9/18/20 10:38 AM, Grygorii Strashko wrote:
> Add DT node for The TI j7200 MCU SoC Gigabit Ethernet two ports Switch
> subsystem (MCU CPSW NUSS).

nit, %s/j7200/J7200/ on this patch and the next.

regards
Suman

> 
> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 74 +++++++++++++++++++
>  1 file changed, 74 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> index 7ecdfdb46436..a994276a8b3d 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> @@ -34,6 +34,20 @@
>  		};
>  	};
>  
> +	mcu_conf: syscon@40f00000 {
> +		compatible = "syscon", "simple-mfd";
> +		reg = <0x0 0x40f00000 0x0 0x20000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x0 0x0 0x40f00000 0x20000>;
> +
> +		phy_gmii_sel: phy@4040 {
> +			compatible = "ti,am654-phy-gmii-sel";
> +			reg = <0x4040 0x4>;
> +			#phy-cells = <1>;
> +		};
> +	};
> +
>  	chipid@43000014 {
>  		compatible = "ti,am654-chipid";
>  		reg = <0x00 0x43000014 0x00 0x4>;
> @@ -136,4 +150,64 @@
>  			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
>  		};
>  	};
> +
> +	mcu_cpsw: ethernet@46000000 {
> +		compatible = "ti,j721e-cpsw-nuss";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		reg = <0x0 0x46000000 0x0 0x200000>;
> +		reg-names = "cpsw_nuss";
> +		ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
> +		dma-coherent;
> +		clocks = <&k3_clks 18 21>;
> +		clock-names = "fck";
> +		power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
> +
> +		dmas = <&mcu_udmap 0xf000>,
> +		       <&mcu_udmap 0xf001>,
> +		       <&mcu_udmap 0xf002>,
> +		       <&mcu_udmap 0xf003>,
> +		       <&mcu_udmap 0xf004>,
> +		       <&mcu_udmap 0xf005>,
> +		       <&mcu_udmap 0xf006>,
> +		       <&mcu_udmap 0xf007>,
> +		       <&mcu_udmap 0x7000>;
> +		dma-names = "tx0", "tx1", "tx2", "tx3",
> +			    "tx4", "tx5", "tx6", "tx7",
> +			    "rx";
> +
> +		ethernet-ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			cpsw_port1: port@1 {
> +				reg = <1>;
> +				ti,mac-only;
> +				label = "port1";
> +				ti,syscon-efuse = <&mcu_conf 0x200>;
> +				phys = <&phy_gmii_sel 1>;
> +			};
> +		};
> +
> +		davinci_mdio: mdio@f00 {
> +			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
> +			reg = <0x0 0xf00 0x0 0x100>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&k3_clks 18 21>;
> +			clock-names = "fck";
> +			bus_freq = <1000000>;
> +		};
> +
> +		cpts@3d000 {
> +			compatible = "ti,am65-cpts";
> +			reg = <0x0 0x3d000 0x0 0x400>;
> +			clocks = <&k3_clks 18 2>;
> +			clock-names = "cpts";
> +			interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "cpts";
> +			ti,cpts-ext-ts-inputs = <4>;
> +			ti,cpts-periodic-outputs = <2>;
> +		};
> +	};
>  };
> 

[PATCH v3 4/4] arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defs

[Grygorii Strashko]

The TI j7200 EVM base board has TI DP83867 PHY connected to external CPSW
NUSS Port 1 in rgmii-rxid mode.

Hence, add pinmux and Ethernet PHY configuration for TI j7200 SoC MCU
Gigabit Ethernet two ports Switch subsystem (CPSW NUSS).

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 .../dts/ti/k3-j7200-common-proc-board.dts     | 45 +++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index e27069317c4e..f7e6b9b5ef5f 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "k3-j7200-som-p0.dtsi"
+#include <dt-bindings/net/ti-dp83867.h>
 
 / {
 	chosen {
@@ -14,6 +15,32 @@
 	};
 };
 
+&wkup_pmx0 {
+	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
+			J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
+			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
+			J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
+			J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
+			J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
+			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
+			J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
+			J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
+			J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
+			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
+			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
+		>;
+	};
+
+	mcu_mdio_pins_default: mcu-mdio1-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
+			J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
+		>;
+	};
+};
+
 &wkup_uart0 {
 	/* Wakeup UART is used by System firmware */
 	status = "disabled";
@@ -62,3 +89,21 @@
 	/* UART not brought out */
 	status = "disabled";
 };
+
+&mcu_cpsw {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+};
+
+&davinci_mdio {
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+	};
+};
+
+&cpsw_port1 {
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&phy0>;
+};
-- 
2.17.1