From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C21BDC2D0E2 for ; Tue, 22 Sep 2020 20:28:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5195A2388B for ; Tue, 22 Sep 2020 20:28:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600806538; bh=qlAGB8Qr8GdJzrbsY5ZDAzLoTSlASP68ZaXdnJTyX4w=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=flwmAVP6mMVxtIHG7UNBPdGhJvaoYX0Alz7U53LjKe0dsyOOku7ZE087C5KiD2TO0 nFs7mdDXAMLdiRfvw2PKrMYwK49qwEw9OJIecXDFLcuctkGaz91Z3byor4uJgpPyEL V4tGOSGsJ1gqlBtyDj6EcyxCEL8XuiF5JusC5SHg= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726589AbgIVU25 (ORCPT ); Tue, 22 Sep 2020 16:28:57 -0400 Received: from mail-il1-f193.google.com ([209.85.166.193]:44849 "EHLO mail-il1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726567AbgIVU25 (ORCPT ); Tue, 22 Sep 2020 16:28:57 -0400 Received: by mail-il1-f193.google.com with SMTP id y8so18286122ilm.11; Tue, 22 Sep 2020 13:28:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=sG3/4Sm2TbdfoNZTEErI9bYJSMt9tAsj3PNbFfGW440=; b=WJ1NhZqoAsaNrOLSJNdkJbrmBNluYYy0JVKh8mHIzM2HO8xBxhNwZKyXT4Cm/5evkA nuaBB3wUuj2LVc4P0qXnBIUMWXnsPTgFh8yVvQr7W4CXLVBh3sOESq/yu5gt2fezn+H7 d3pGncXLKtlAwEIYIj5FBDwGIftkDrN+K8lUDaI1Sl+aloCJk5Zc30xidv0QZoU1Mfq9 6EcCnLLonzCgZ2JMsebX/QFFv+aEFIe+EbwpoumWjyaSRPIswPAfsPJu6UN5C97HY78r PvHJjS7FmVFPdPdGzrbYPKXfuEfKwJnQPxKPvI9IJ+y0biOSiGvStNmnVhwbjkuCVZy6 g2+g== X-Gm-Message-State: AOAM530b66ngV7Q23NCSykeXRG9WeG1izwPC/PH6XICwy/ecpKqEW42S 1dZu8qhCJY4r1L5xw0BFMw== X-Google-Smtp-Source: ABdhPJwa0z2waMXySa0O+m+dIuO8EDFkC94aAPAWjkmJ8FNwkvzwEn3oTHwvj7PfsYkpPqkQ+KyLPg== X-Received: by 2002:a92:99cb:: with SMTP id t72mr5775658ilk.172.1600806535543; Tue, 22 Sep 2020 13:28:55 -0700 (PDT) Received: from xps15 ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id u15sm7898833ior.6.2020.09.22.13.28.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2020 13:28:54 -0700 (PDT) Received: (nullmailer pid 3186311 invoked by uid 1000); Tue, 22 Sep 2020 20:28:52 -0000 Date: Tue, 22 Sep 2020 14:28:52 -0600 From: Rob Herring To: Hector Yuan Cc: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, "Rafael J. Wysocki" , Viresh Kumar , linux-kernel@vger.kernel.org, wsd_upstream@mediatek.com Subject: Re: [PATCH v7 2/2] dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW Message-ID: <20200922202852.GA3134161@bogus> References: <1599712262-8819-1-git-send-email-hector.yuan@mediatek.com> <1599712262-8819-3-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1599712262-8819-3-git-send-email-hector.yuan@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Sep 10, 2020 at 12:31:02PM +0800, Hector Yuan wrote: > From: "Hector.Yuan" > > Add devicetree bindings for MediaTek HW driver. > > Signed-off-by: Hector.Yuan > --- > .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 141 ++++++++++++++++++++ > 1 file changed, 141 insertions(+) > create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > new file mode 100644 > index 0000000..118a163 > --- /dev/null > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > @@ -0,0 +1,141 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek's CPUFREQ Bindings > + > +maintainers: > + - Hector Yuan > + > +description: > + CPUFREQ HW is a hardware engine used by MediaTek > + SoCs to manage frequency in hardware. It is capable of controlling frequency > + for multiple clusters. > + > +properties: > + compatible: > + const: "mediatek,cpufreq-hw" Needs to be SoC specific. This stuff is never constant from one SoC to the next. 'cpufreq' is a Linuxism. What's the block called in the datasheet? Use that. Don't need quotes either. > + > + reg: > + minItems: 1 > + maxItems: 2 > + description: | > + Addresses and sizes for the memory of the HW bases in each frequency domain. > + > + reg-names: > + items: > + - const: "freq-domain0" > + - const: "freq-domain1" Kind of pointless to have names based on the index. Drop 'reg-names'. > + description: | > + Frequency domain name. i.e. > + "freq-domain0", "freq-domain1". > + > + "#freq-domain-cells": > + const: 1 > + description: | > + Number of cells in a freqency domain specifier. You don't need this. It's not a common binding that's going to vary. > + > + mtk-freq-domain: > + maxItems: 1 > + description: | > + Define this cpu belongs to which frequency domain. i.e. > + cpu0-3 belong to frequency domain0, > + cpu4-6 belong to frequency domain1. This property doesn't go in the 'mediatek,cpufreq-hw' node. You would need a separate schema. However, I think the easiest thing to do here is something like this: mediatek,freq-domain-0 = <&cpu0>, <&cpu1>; Or you could just re-use the OPP binding with just 0 entries: opp-table-0 { compatible = "mediatek,hw-operating-points", "operating-points-v2"; }; opp-table-1 { compatible = "mediatek,hw-operating-points", "operating-points-v2"; }; > + > +required: > + - compatible > + - reg > + - reg-names > + - "#freq-domain-cells" > + > +examples: > + - | > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 0>; > + reg = <0x000>; > + }; > + > + cpu1: cpu@1 { Unit address is wrong. > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 0>; > + reg = <0x100>; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 0>; > + reg = <0x200>; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 0>; > + reg = <0x300>; > + }; > + > + cpu4: cpu@4 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 1>; > + reg = <0x400>; > + }; > + > + cpu5: cpu@5 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 1>; > + reg = <0x500>; > + }; > + > + cpu6: cpu@6 { > + device_type = "cpu"; > + compatible = "arm,cortex-a75"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 1>; > + reg = <0x600>; > + }; > + > + cpu7: cpu@7 { > + device_type = "cpu"; > + compatible = "arm,cortex-a75"; > + enable-method = "psci"; > + mtk-freq-domain = <&cpufreq_hw 1>; > + reg = <0x700>; > + }; > + }; > + > + /* ... */ > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpufreq_hw: cpufreq@11bc00 { > + compatible = "mediatek,cpufreq-hw"; > + reg = <0 0x11bc10 0 0x8c>, > + <0 0x11bca0 0 0x8c>; > + reg-names = "freq-domain0", "freq-domain1"; > + #freq-domain-cells = <1>; > + }; > + }; > + > + > + > + > -- > 1.7.9.5