From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48719C2D0A8 for ; Wed, 23 Sep 2020 15:57:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0C60623119 for ; Wed, 23 Sep 2020 15:57:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600876624; bh=wK5xYGCPPfUs8+41Dz9ipS8t+iEHvruvK+B7KturTjE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=jw2gYb8DL39t3OtX5N2TfDSMyXCxi8JeSfQUEHU9JyWABGDU9SKyc45McODdZCC9q QQxCS4dUeoOmvfTxX7Yff4OH7PRvR4oVDG0nXyPryZqXO1T/nHSHXndNgZk3RjLgM+ IbVG7fGj+UFE0Ca8FnMQyHGtP7cxJU1UK0trZG/g= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726156AbgIWP5D (ORCPT ); Wed, 23 Sep 2020 11:57:03 -0400 Received: from mail-il1-f194.google.com ([209.85.166.194]:38254 "EHLO mail-il1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726130AbgIWP5D (ORCPT ); Wed, 23 Sep 2020 11:57:03 -0400 Received: by mail-il1-f194.google.com with SMTP id t18so89912ilp.5; Wed, 23 Sep 2020 08:57:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=hprSGRETocdQf78XETYgy258w0hwpUnZV3tfOx1jhyw=; b=svIVldVq9lHc5+x5TRugBYQGLkCd1noQWKci2+n/cuJyGhzw0pq1j1pkesuQVb6Iya UxN6cGHmRGwMmyJc8VxkkqGFDMijlgyG7kJE5M5YOMvN1Z3uhKq+w7JAfmZuH1+NM0Y/ //nTmuNm1QbUt2MkOsBW4jEOFycag9PPx+DfOxwFtOJ5SS6MHA/I95pdmgyq4nn6T35s Lh3HLJ9CfKunbpTgsmONs56jZXGTPC+nlyjzFDBte2q0oedlm1AvIfdyAteinZ5kHep/ 2bTC7MiswTa1eyDQWC/EIKd3hycL72n400KTzgP9i+JQ88GF8GIpYm7501a5OtukjW+f dbkA== X-Gm-Message-State: AOAM531DnCzwYpJ15E9dr3nHGHWCkXyNTa1jEmuSj3lIUvI+6AC+v/O6 oR9bz8hvbBIptTcm0UvViA== X-Google-Smtp-Source: ABdhPJwF7cW7wtVVPFcinJZJ2wi7GujCzMGUvUKlTAUpRG7xH9KI47JiB3sor9fbqqkTDEEEDRoQKQ== X-Received: by 2002:a92:d8cb:: with SMTP id l11mr371869ilo.271.1600876622055; Wed, 23 Sep 2020 08:57:02 -0700 (PDT) Received: from xps15 ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id p5sm18530ilg.32.2020.09.23.08.57.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 08:57:01 -0700 (PDT) Received: (nullmailer pid 825904 invoked by uid 1000); Wed, 23 Sep 2020 15:57:00 -0000 Date: Wed, 23 Sep 2020 09:57:00 -0600 From: Rob Herring To: Kunihiko Hayashi Cc: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Murali Karicheri , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: Re: [PATCH 2/3] PCI: dwc: Add common iATU register support Message-ID: <20200923155700.GA820801@bogus> References: <1599814203-14441-1-git-send-email-hayashi.kunihiko@socionext.com> <1599814203-14441-3-git-send-email-hayashi.kunihiko@socionext.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1599814203-14441-3-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Sep 11, 2020 at 05:50:02PM +0900, Kunihiko Hayashi wrote: > This gets iATU register area from reg property that has reg-names "atu". > In Synopsys DWC version 4.80 or later, since iATU register area is > separated from core register area, this area is necessary to get from > DT independently. > > Cc: Murali Karicheri > Cc: Jingoo Han > Cc: Gustavo Pimentel > Suggested-by: Rob Herring > Signed-off-by: Kunihiko Hayashi > --- > drivers/pci/controller/dwc/pcie-designware.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 4d105ef..4a360bc 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -10,6 +10,7 @@ > > #include > #include > +#include > #include > > #include "../../pci.h" > @@ -526,11 +527,16 @@ void dw_pcie_setup(struct dw_pcie *pci) > u32 val; > struct device *dev = pci->dev; > struct device_node *np = dev->of_node; > + struct platform_device *pdev; > > if (pci->version >= 0x480A || (!pci->version && > dw_pcie_iatu_unroll_enabled(pci))) { > pci->iatu_unroll_enabled = true; > - if (!pci->atu_base) > + pdev = of_find_device_by_node(np); Use to_platform_device(dev) instead. Put that at the beginning as I'm going to move 'dbi' in here too. > + if (!pci->atu_base && pdev) > + pci->atu_base = > + devm_platform_ioremap_resource_byname(pdev, "atu"); > + if (IS_ERR_OR_NULL(pci->atu_base)) > pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; > } > dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? > -- > 2.7.4 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel