From: Jacky Bai <ping.bai@nxp.com>
To: shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de,
krzk@kernel.org
Cc: festevam@gmail.com, linux-imx@nxp.com, devicetree@vger.kernel.org
Subject: [PATCH v2 1/2] arm64: dts: freescale: Add pmu support on imx8mp
Date: Tue, 29 Sep 2020 17:15:22 +0800 [thread overview]
Message-ID: <20200929091523.2775950-1-ping.bai@nxp.com> (raw)
Add PMU node to enable pmu support on imx8mp.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
---
Change in V2:
- Update the compatible string to ca53 specific
- Correct the GIC_CPU_MASK num to 4 as only have 4xA53 cores
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 6038f66aefc1..2a7bbd4d68ac 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -133,6 +133,13 @@ clk_ext4: clock-ext4 {
clock-output-names = "clk_ext4";
};
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
--
2.26.2
next reply other threads:[~2020-09-29 9:09 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-29 9:15 Jacky Bai [this message]
2020-09-29 9:15 ` [PATCH v2 2/2] arm64: dts: freescale: Add pmu support on imx8mn Jacky Bai
2020-09-29 9:26 ` Krzysztof Kozlowski
2020-09-29 9:26 ` [PATCH v2 1/2] arm64: dts: freescale: Add pmu support on imx8mp Krzysztof Kozlowski
2020-10-30 0:55 ` Shawn Guo
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