Re: [PATCH v2 devicetree 2/2] powerpc: dts: t1040rdb: add ports for Seville Ethernet switch

Maxim Kochetkov
2020-09-29T13:12:02Z

Reviewed-by: Maxim Kochetkov <fido_max@inbox.ru>

29.09.2020 14:32, Vladimir Oltean пишет:
> From: Vladimir Oltean <olteanv@gmail.com>
>
> Define the network interface names for the switch ports and hook them up
> to the 2 QSGMII PHYs that are onboard.
>
> A conscious decision was taken to go along with the numbers that are
> written on the front panel of the board and not with the hardware
> numbers of the switch chip ports. The 2 numbering schemes are
> shifted by 8.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> Changes in v2:
> Use the existing way of accessing the mdio bus and not labels.
>
> arch/powerpc/boot/dts/fsl/t1040rdb.dts | 115 +++++++++++++++++++++++++
> 1 file changed, 115 insertions(+)
>
> diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb.dts b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
> index 65ff34c49025..3fd08a2b6dcb 100644
> --- a/arch/powerpc/boot/dts/fsl/t1040rdb.dts
> +++ b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
> @@ -64,6 +64,40 @@ mdio@fc000 {
> phy_sgmii_2: ethernet-phy@3 {
> reg = <0x03>;
> };
> +
> + /* VSC8514 QSGMII PHY */
> + phy_qsgmii_0: ethernet-phy@4 {
> + reg = <0x4>;
> + };
> +
> + phy_qsgmii_1: ethernet-phy@5 {
> + reg = <0x5>;
> + };
> +
> + phy_qsgmii_2: ethernet-phy@6 {
> + reg = <0x6>;
> + };
> +
> + phy_qsgmii_3: ethernet-phy@7 {
> + reg = <0x7>;
> + };
> +
> + /* VSC8514 QSGMII PHY */
> + phy_qsgmii_4: ethernet-phy@8 {
> + reg = <0x8>;
> + };
> +
> + phy_qsgmii_5: ethernet-phy@9 {
> + reg = <0x9>;
> + };
> +
> + phy_qsgmii_6: ethernet-phy@a {
> + reg = <0xa>;
> + };
> +
> + phy_qsgmii_7: ethernet-phy@b {
> + reg = <0xb>;
> + };
> };
> };
> };
> @@ -76,3 +110,84 @@ cpld@3,0 {
> };
>
> #include "t1040si-post.dtsi"
> +
> +&seville_switch {
> + status = "okay";
> +};
> +
> +&seville_port0 {
> + managed = "in-band-status";
> + phy-handle = <&phy_qsgmii_0>;
> + phy-mode = "qsgmii";
> + /* ETH4 written on chassis */
> + label = "swp4";
> + status = "okay";
> +};
> +
> +&seville_port1 {
> + managed = "in-band-status";
> + phy-handle = <&phy_qsgmii_1>;
> + phy-mode = "qsgmii";
> + /* ETH5 written on chassis */
> + label = "swp5";
> + status = "okay";
> +};
> +
> +&seville_port2 {
> + managed = "in-band-status";
> + phy-handle = <&phy_qsgmii_2>;
> + phy-mode = "qsgmii";
> + /* ETH6 written on chassis */
> + label = "swp6";
> + status = "okay";
> +};
> +
> +&seville_port3 {
> + managed = "in-band-status";
> + phy-handle = <&phy_qsgmii_3>;
> + phy-mode = "qsgmii";
> + /* ETH7 written on chassis */
> + label = "swp7";
> + status = "okay";
> +};
> +
> +&seville_port4 {
> + managed = "in-band-status";
> + phy-handle = <&phy_qsgmii_4>;
> + phy-mode = "qsgmii";
> + /* ETH8 written on chassis */
> + label = "swp8";
> + status = "okay";
> +};
> +
> +&seville_port5 {
> + managed = "in-band-status";
> + phy-handle = <&phy_qsgmii_5>;
> + phy-mode = "qsgmii";
> + /* ETH9 written on chassis */
> + label = "swp9";
> + status = "okay";
> +};
> +
> +&seville_port6 {
> + managed = "in-band-status";
> + phy-handle = <&phy_qsgmii_6>;
> + phy-mode = "qsgmii";
> + /* ETH10 written on chassis */
> + label = "swp10";
> + status = "okay";
> +};
> +
> +&seville_port7 {
> + managed = "in-band-status";
> + phy-handle = <&phy_qsgmii_7>;
> + phy-mode = "qsgmii";
> + /* ETH11 written on chassis */
> + label = "swp11";
> + status = "okay";
> +};
> +
> +&seville_port8 {
> + ethernet = <&enet0>;
> + status = "okay";
> +};
>