From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6177AC4363D for ; Fri, 2 Oct 2020 11:10:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2DEA2206B8 for ; Fri, 2 Oct 2020 11:10:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1601637029; bh=ipDhpDRZbtV67DJHpXhpbwyoadzpTea9ToXi37IRTAA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=rlma+3L3fVon8agwoZz8xacW+blj+6MYoFouayrwFLsHdU04UiCul0GnwFLff73SU S6AMFVaXvWFU+IHRw/GyMCQDZWQ/JFbUoBri/fgt60sIVCKzogsmSKeE+ZuH+yJJFv aD4PdexST2aPtLzJ/oFEMaMHJgl6b+aaMgmQoKcA= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725953AbgJBLKW (ORCPT ); Fri, 2 Oct 2020 07:10:22 -0400 Received: from mail-ej1-f65.google.com ([209.85.218.65]:35056 "EHLO mail-ej1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726010AbgJBLKU (ORCPT ); Fri, 2 Oct 2020 07:10:20 -0400 Received: by mail-ej1-f65.google.com with SMTP id u21so1411012eja.2; Fri, 02 Oct 2020 04:10:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=wDTKbdGBT6DJY0L4YlF2VzawALLmfAUZKYoHRF2W8hw=; b=hXroNN/mFxQJUDMMFc5Z7u97dUzd8NTuSEGTPkcvUzeM1mpAjV/oZKmGZ1LHHk96W/ QD3mrCP9ilG3ZBhvonoXJUN28gt/4xLkT3I8qSN0lxhfCr/gFQJ/xlWOBcdKJF7+lsS9 I2UJImiGv3zRI5fEgP+/4xD5CRsCh6Z+be/HAY3WzhUdXGj/nx9nZoHbwBR4+lGcUemn B/8LG3B81aUoVCkiYu/sYzwZI2oU2BMYuoL3CBe0sLbciMr25a8lyMqqbtELDDmzmRCH VQ79Aq5biPlkqQtYNrvCnKN0nvm9d0/u7jxQh2m2ycWkfc3/1p4R7OQW5/Ow+4bi9DDD r5Ow== X-Gm-Message-State: AOAM533ZZiu7fVlSaNXf+X6fsmmvCs0zRFFbSXXz0EbjwttXS1I1t4kG 7xQBG6JQvMKkE5739Hkpsec= X-Google-Smtp-Source: ABdhPJyr+lz9aljZjSALIJLlmHUZmvPOwMjCcDNc2vDAAzSqnPdX/49XBEEsx1dw9329gDRVFsjj5w== X-Received: by 2002:a17:906:2dd7:: with SMTP id h23mr302773eji.175.1601637018319; Fri, 02 Oct 2020 04:10:18 -0700 (PDT) Received: from pi3 ([194.230.155.194]) by smtp.googlemail.com with ESMTPSA id v25sm906385edr.29.2020.10.02.04.10.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Oct 2020 04:10:17 -0700 (PDT) Date: Fri, 2 Oct 2020 13:10:14 +0200 From: Krzysztof Kozlowski To: Yong Wu Cc: Joerg Roedel , Matthias Brugger , Rob Herring , Robin Murphy , Will Deacon , Evan Green , Tomasz Figa , linux-mediatek@lists.infradead.org, srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, youlin.pei@mediatek.com, Nicolas Boichat , anan.sun@mediatek.com, chao.hao@mediatek.com, ming-fan.chen@mediatek.com, Greg Kroah-Hartman , kernel-team@android.com Subject: Re: [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU Message-ID: <20201002111014.GE6888@pi3> References: <20200930070647.10188-1-yong.wu@mediatek.com> <20200930070647.10188-7-yong.wu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20200930070647.10188-7-yong.wu@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Sep 30, 2020 at 03:06:29PM +0800, Yong Wu wrote: > This patch adds decriptions for mt8192 IOMMU and SMI. > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > table format. The M4U-SMI HW diagram is as below: > > EMI > | > M4U > | > ------------ > SMI Common > ------------ > | > +-------+------+------+----------------------+-------+ > | | | | ...... | | > | | | | | | > larb0 larb1 larb2 larb4 ...... larb19 larb20 > disp0 disp1 mdp vdec IPE IPE > > All the connections are HW fixed, SW can NOT adjust it. > > mt8192 M4U support 0~16GB iova range. we preassign different engines > into different iova ranges: > > domain-id module iova-range larbs > 0 disp 0 ~ 4G larb0/1 > 1 vcodec 4G ~ 8G larb4/5/7 > 2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 > 3 CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10 > 4 CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5 > > The iova range for CCU0/1(camera control unit) is HW requirement. > > Signed-off-by: Yong Wu > Reviewed-by: Rob Herring > --- > .../bindings/iommu/mediatek,iommu.yaml | 9 +- > .../mediatek,smi-common.yaml | 5 +- > .../memory-controllers/mediatek,smi-larb.yaml | 3 +- > include/dt-bindings/memory/mt8192-larb-port.h | 239 ++++++++++++++++++ > 4 files changed, 251 insertions(+), 5 deletions(-) > create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h I see it depends on previous patches but does it have to be within one commit? Is it not bisectable? The memory changes/bindings could go via memory tree if this is split. Best regards, Krzysztof