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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id m7sm1486436otk.74.2020.10.06.12.42.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Oct 2020 12:42:15 -0700 (PDT) Received: (nullmailer pid 2707920 invoked by uid 1000); Tue, 06 Oct 2020 19:42:14 -0000 Date: Tue, 6 Oct 2020 14:42:14 -0500 From: Rob Herring To: Lucas Stach Cc: Shawn Guo , NXP Linux Team , Fabio Estevam , Frieder Schrempf , Marek Vasut , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, kernel@pengutronix.de, patchwork-lst@pengutronix.de Subject: Re: [PATCH 07/11] soc: imx: gpcv2: add support for optional resets Message-ID: <20201006194214.GA2702908@bogus> References: <20200930155006.535712-1-l.stach@pengutronix.de> <20200930155006.535712-8-l.stach@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200930155006.535712-8-l.stach@pengutronix.de> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Sep 30, 2020 at 05:50:02PM +0200, Lucas Stach wrote: > Normally the reset for the devices inside the power domain is > triggered automatically from the PGC in the power-up sequencing, > however on i.MX8MM this doesn't work for the GPU power domains. > > Add support for triggering the reset explicitly during the power > up sequencing. > > Signed-off-by: Lucas Stach > --- > .../devicetree/bindings/power/fsl,imx-gpcv2.yaml | 6 ++++++ > drivers/soc/imx/gpcv2.c | 13 +++++++++++++ > 2 files changed, 19 insertions(+) > > diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml > index bde09a0b2da3..9773771b9000 100644 > --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml > +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml > @@ -62,6 +62,12 @@ properties: > > power-supply: true > > + resets: > + description: | > + A number of phandles to resets that need to be asserted during > + power-up sequencing of the domain. > + minItems: 1 What's the max? It's going to default to 1 if you don't say. > + > required: > - '#power-domain-cells' > - reg > diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c > index db93fef0c76b..76aa8a67d8a7 100644 > --- a/drivers/soc/imx/gpcv2.c > +++ b/drivers/soc/imx/gpcv2.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -112,6 +113,7 @@ struct imx_pgc_domain { > struct regulator *regulator; > struct clk *clk[GPC_CLK_MAX]; > int num_clks; > + struct reset_control *reset; > > unsigned int pgc; > > @@ -167,6 +169,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) > } > } > > + reset_control_assert(domain->reset); > + > if (domain->bits.pxx) { > /* request the domain to power up */ > regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, > @@ -189,6 +193,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) > GPC_PGC_CTRL_PCR, 0); > } > > + reset_control_deassert(domain->reset); > + > /* request the ADB400 to power up */ > if (domain->bits.hskreq) { > regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, > @@ -577,6 +583,13 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) > domain->voltage, domain->voltage); > } > > + domain->reset = devm_reset_control_array_get_optional_exclusive(domain->dev); > + if (IS_ERR(domain->reset)) { > + if (PTR_ERR(domain->reset) != -EPROBE_DEFER) > + dev_err(domain->dev, "Failed to get domain's reset\n"); > + return PTR_ERR(domain->reset); > + } > + > ret = imx_pgc_get_clocks(domain); > if (ret) { > if (ret != -EPROBE_DEFER) > -- > 2.20.1 >