Re: [PATCH] dt-bindings: clock: adi,axi-clkgen: convert old binding to yaml format

[Rob Herring <robh@kernel.org>]

On Thu, Oct 01, 2020 at 11:50:35AM +0300, Alexandru Ardelean wrote:
> This change converts the old binding for the AXI clkgen driver to a yaml
> format.
> 
> As maintainers, added:
>  - Lars-Peter Clausen <lars@metafoo.de> - as original author of driver &
>    binding

Do you have permission for relicensing? The default was GPL-2.0.

>  - Michael Hennerich <michael.hennerich@analog.com> - as supporter of
>    Analog Devices drivers
> 
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> ---
>  .../bindings/clock/adi,axi-clkgen.yaml        | 52 +++++++++++++++++++
>  .../devicetree/bindings/clock/axi-clkgen.txt  | 25 ---------
>  2 files changed, 52 insertions(+), 25 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml
>  delete mode 100644 Documentation/devicetree/bindings/clock/axi-clkgen.txt
> 
> diff --git a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml
> new file mode 100644
> index 000000000000..45497f370cb3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Binding for Analog Devices AXI clkgen pcore clock generator
> +
> +maintainers:
> +  - Lars-Peter Clausen <lars@metafoo.de>
> +  - Michael Hennerich <michael.hennerich@analog.com>
> +
> +description: |
> +  The axi_clkgen IP core is a software programmable clock generator,
> +  that can be synthesized on various FPGA platforms.
> +
> +  Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen
> +
> +properties:
> +  compatible:
> +    enum:
> +      - adi,axi-clkgen-2.00.a
> +
> +  clocks:
> +    description:
> +      Phandle and clock specifier for the parent clock(s). 

Drop, that's every 'clocks'.

> This must either
> +      reference one clock if only the first clock input is connected or two
> +      if both clock inputs are connected. For the later case the clock
> +      connected to the first input must be specified first.

That doesn't really say what the 2 clocks are.

> +    minItems: 1
> +    maxItems: 2
> +
> +  '#clock-cells':
> +    const: 0
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - '#clock-cells'

additionalProperties: false

> +
> +examples:
> +  - |
> +    clock@ff000000 {

clock-controller@...

> +      compatible = "adi,axi-clkgen-2.00.a";
> +      #clock-cells = <0>;
> +      reg = <0xff000000 0x1000>;
> +      clocks = <&osc 1>;
> +    };
> diff --git a/Documentation/devicetree/bindings/clock/axi-clkgen.txt b/Documentation/devicetree/bindings/clock/axi-clkgen.txt
> deleted file mode 100644
> index aca94fe9416f..000000000000
> --- a/Documentation/devicetree/bindings/clock/axi-clkgen.txt
> +++ /dev/null
> @@ -1,25 +0,0 @@
> -Binding for the axi-clkgen clock generator
> -
> -This binding uses the common clock binding[1].
> -
> -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> -
> -Required properties:
> -- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
> -- #clock-cells : from common clock binding; Should always be set to 0.
> -- reg : Address and length of the axi-clkgen register set.
> -- clocks : Phandle and clock specifier for the parent clock(s). This must
> -	either reference one clock if only the first clock input is connected or two
> -	if both clock inputs are connected. For the later case the clock connected
> -	to the first input must be specified first.
> -
> -Optional properties:
> -- clock-output-names : From common clock binding.
> -
> -Example:
> -	clock@ff000000 {
> -		compatible = "adi,axi-clkgen";
> -		#clock-cells = <0>;
> -		reg = <0xff000000 0x1000>;
> -		clocks = <&osc 1>;
> -	};
> -- 
> 2.17.1
>