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[69.120.86.51]) by smtp.gmail.com with ESMTPSA id 128sm2408554qkm.76.2020.10.07.14.46.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Oct 2020 14:46:35 -0700 (PDT) Date: Wed, 7 Oct 2020 17:46:33 -0400 From: Vivek Unune To: Andrew Lunn Cc: devicetree@vger.kernel.org, Hauke Mehrtens , =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= , linux-kernel@vger.kernel.org, Rob Herring , bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 1/3] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl Message-ID: <20201007214633.GA1972@ubuntu> References: <6687de05226dd055ee362933d4841a12b038792d.1601655904.git.npcomplete13@gmail.com> <20201007210134.GD112961@lunn.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201007210134.GD112961@lunn.ch> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Oct 07, 2020 at 11:01:34PM +0200, Andrew Lunn wrote: > On Wed, Oct 07, 2020 at 03:01:50PM -0400, Vivek Unune wrote: > > Forgo the use of mmioreg mdio mux infavor of the pinctrl > > Hi Vivek > > Could you add some more details please. I don't know this > hardware. I'm assuming there are two MDIO busses, external as talked > about in the comments, and an internal one? And for this hardware you > only need one of them? But i don't see what pinmux has to do with > this? Hi Andrew, There are indeed two mdio busses. To access the external bus, 9th bit of the mdio register has to be set. And to enable mii function, one has to set the registers 6 & 7 which is part of the pin controller. Earlier the pin controller was not defined and I resorted to use a combination of memory mapped io mux to change desired bits. Now that we have a pin controller - which is resposnsible for other functionality such as pwm, i2c, uart2, it makes sense to have a consistent device tree Hope this helps, Vivek > > Thanks > Andrew >