From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org
Subject: [PATCH] arm64: dts: sm8250: add iommus entry to QUP nodes
Date: Sat, 10 Oct 2020 16:21:25 +0300 [thread overview]
Message-ID: <20201010132125.416064-1-dmitry.baryshkov@linaro.org> (raw)
Enable IOMMUs configuration for QUP nodes to stop SM8250 boards from
rebooting when using I2C DMA transfers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 889d11725c5d..ec6cfaaaa971 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -468,6 +468,7 @@ qupv3_id_2: geniqup@8c0000 {
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
+ iommus = <&apps_smmu 0x63 0x0>;
ranges;
status = "disabled";
@@ -674,6 +675,7 @@ qupv3_id_0: geniqup@9c0000 {
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
+ iommus = <&apps_smmu 0x5a3 0x0>;
ranges;
status = "disabled";
@@ -936,6 +938,7 @@ qupv3_id_1: geniqup@ac0000 {
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
+ iommus = <&apps_smmu 0x43 0x0>;
ranges;
status = "disabled";
--
2.28.0
reply other threads:[~2020-10-10 23:09 UTC|newest]
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