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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id y13sm25534ote.45.2020.10.13.08.42.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2020 08:42:36 -0700 (PDT) Received: (nullmailer pid 3571584 invoked by uid 1000); Tue, 13 Oct 2020 15:42:36 -0000 Date: Tue, 13 Oct 2020 10:42:36 -0500 From: Rob Herring To: "Chrisanthus, Anitha" Cc: Neil Armstrong , "dri-devel@lists.freedesktop.org" , "devicetree@vger.kernel.org" , "Vetter, Daniel" , "Dea, Edmund J" , "sam@ravnborg.org" Subject: Re: [PATCH v9 1/5] dt-bindings: display: Add support for Intel KeemBay Display Message-ID: <20201013154236.GA3562909@bogus> References: <1602205443-9036-1-git-send-email-anitha.chrisanthus@intel.com> <1602205443-9036-2-git-send-email-anitha.chrisanthus@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Oct 13, 2020 at 12:24:38AM +0000, Chrisanthus, Anitha wrote: > Hi Neil, > > Thanks for your review, please see my reply inline. > > > -----Original Message----- > > From: Neil Armstrong > > Sent: Friday, October 9, 2020 2:10 AM > > To: Chrisanthus, Anitha ; dri- > > devel@lists.freedesktop.org; devicetree@vger.kernel.org; Vetter, Daniel > > > > Cc: Dea, Edmund J ; sam@ravnborg.org > > Subject: Re: [PATCH v9 1/5] dt-bindings: display: Add support for Intel > > KeemBay Display > > > > Hi, > > > > On 09/10/2020 03:03, Anitha Chrisanthus wrote: > > > This patch adds bindings for Intel KeemBay Display > > > > > > v2: review changes from Rob Herring > > > > > > Signed-off-by: Anitha Chrisanthus > > > --- > > > .../bindings/display/intel,keembay-display.yaml | 99 > > ++++++++++++++++++++++ > > > 1 file changed, 99 insertions(+) > > > create mode 100644 > > Documentation/devicetree/bindings/display/intel,keembay-display.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/display/intel,keembay- > > display.yaml b/Documentation/devicetree/bindings/display/intel,keembay- > > display.yaml > > > new file mode 100644 > > > index 0000000..a38493d > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/display/intel,keembay- > > display.yaml > > > @@ -0,0 +1,99 @@ > > > +# SPDX-License-Identifier: GPL-2.0-only > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/display/intel,keembay- > > display.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Devicetree bindings for Intel Keem Bay display controller > > > + > > > +maintainers: > > > + - Anitha Chrisanthus > > > + - Edmond J Dea > > > + > > > +properties: > > > + compatible: > > > + const: intel,kmb_display > > > + > > > + reg: > > > + items: > > > + - description: Lcd registers range > > > + - description: Mipi registers range > > > > Looking at the registers, the MIPI transceiver seems to be a separate IP, > > same for D-PHY which should have a proper PHY driver instead of beeing > > handled > > here. > > > The LCD, MIPI DSI, DPHY and MSSCAM as a group, are considered the > display subsystem for Keem Bay. As such, there are several > interdependencies that make splitting them up next to impossible and Please detail what those inter-dependencies are. It's doubtful that you have anything we have not had to deal with in other SoCs. > currently we do not have the resources available for that effort. That is certainly not justification for accepting this. Rob