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Fri, 23 Oct 2020 02:34:51 -0700 (PDT) Received: from kozik-lap ([194.230.155.171]) by smtp.googlemail.com with ESMTPSA id s12sm498655ejy.25.2020.10.23.02.34.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2020 02:34:49 -0700 (PDT) Date: Fri, 23 Oct 2020 11:34:46 +0200 From: Krzysztof Kozlowski To: Adam Ford Cc: linux-arm-kernel@lists.infradead.org, marex@denx.de, aford@beaconembedded.com, l.stach@pengutronix.de, Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: dts: imx8mm: Add GPU node Message-ID: <20201023093446.GA42872@kozik-lap> References: <20201022171639.773702-1-aford173@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20201022171639.773702-1-aford173@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Oct 22, 2020 at 12:16:39PM -0500, Adam Ford wrote: > According to the documentation from NXP, the i.MX8M Nano has a > Vivante GC7000 Ultra Lite as its GPU core. > > With this patch, the Etnaviv driver presents the GPU as: > etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203 > > It uses the GPCV2 controller to enable the power domain for the GPU. > > Signed-off-by: Adam Ford > --- > This patch depends on a series located: > https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=368903 > and > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > index 605e6dbd2c6f..62c8cd3dea7c 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -4,6 +4,8 @@ > */ > > #include > +#include > +#include > #include > #include > #include > @@ -1019,6 +1021,31 @@ gpmi: nand-controller@33002000 { > status = "disabled"; > }; > > + gpu: gpu@38000000 { > + compatible = "vivante,gc"; > + reg = <0x38000000 0x8000>; > + interrupts = ; > + clocks = <&clk IMX8MN_CLK_GPU_AHB>, > + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MN_CLK_GPU_CORE_ROOT>, > + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; > + clock-names = "reg", "bus", "core", "shader"; > + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>, > + <&clk IMX8MN_CLK_GPU_SHADER_SRC>, > + <&clk IMX8MN_CLK_GPU_AXI>, > + <&clk IMX8MN_CLK_GPU_AHB>, > + <&clk IMX8MN_GPU_PLL>, > + <&clk IMX8MN_CLK_GPU_CORE_DIV>, > + <&clk IMX8MN_CLK_GPU_SHADER_DIV>; > + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, > + <&clk IMX8MN_GPU_PLL_OUT>, > + <&clk IMX8MN_SYS_PLL1_800M>, > + <&clk IMX8MN_SYS_PLL1_800M>; > + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, > + <400000000>, <400000000>; Plaese indent it till '=' and put each entry in new line. This will match other 'assigned-clock' properties. Best regards, Krzysztof