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Tue, 27 Oct 2020 02:15:19 -0700 (PDT) Received: from kozik-lap ([194.230.155.184]) by smtp.googlemail.com with ESMTPSA id t5sm546479edw.45.2020.10.27.02.15.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2020 02:15:18 -0700 (PDT) Date: Tue, 27 Oct 2020 10:15:16 +0100 From: Krzysztof Kozlowski To: Dmitry Osipenko Cc: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: Re: [PATCH v6 22/52] ARM: tegra: Add interconnect properties to Tegra30 device-tree Message-ID: <20201027091516.GA10762@kozik-lap> References: <20201025221735.3062-1-digetx@gmail.com> <20201025221735.3062-23-digetx@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20201025221735.3062-23-digetx@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Oct 26, 2020 at 01:17:05AM +0300, Dmitry Osipenko wrote: > Add interconnect properties to the Memory Controller, External Memory > Controller and the Display Controller nodes in order to describe hardware > interconnection. > > Signed-off-by: Dmitry Osipenko > --- > arch/arm/boot/dts/tegra30.dtsi | 27 ++++++++++++++++++++++++++- > 1 file changed, 26 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi > index aeae8c092d41..2caf6cc6f4b1 100644 > --- a/arch/arm/boot/dts/tegra30.dtsi > +++ b/arch/arm/boot/dts/tegra30.dtsi > @@ -210,6 +210,17 @@ dc@54200000 { > > nvidia,head = <0>; > > + interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>, Does not compile. > + <&mc TEGRA30_MC_DISPLAY0B &emc>, > + <&mc TEGRA30_MC_DISPLAY1B &emc>, > + <&mc TEGRA30_MC_DISPLAY0C &emc>, > + <&mc TEGRA30_MC_DISPLAYHC &emc>; > + interconnect-names = "wina", > + "winb", > + "winb-vfilter", > + "winc", > + "cursor"; > + > rgb { > status = "disabled"; > }; > @@ -229,6 +240,17 @@ dc@54240000 { > > nvidia,head = <1>; > > + interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>, > + <&mc TEGRA30_MC_DISPLAY0BB &emc>, > + <&mc TEGRA30_MC_DISPLAY1BB &emc>, > + <&mc TEGRA30_MC_DISPLAY0CB &emc>, > + <&mc TEGRA30_MC_DISPLAYHCB &emc>; > + interconnect-names = "wina", > + "winb", > + "winb-vfilter", > + "winc", > + "cursor"; > + > rgb { > status = "disabled"; > }; > @@ -748,15 +770,18 @@ mc: memory-controller@7000f000 { > > #iommu-cells = <1>; > #reset-cells = <1>; > + #interconnect-cells = <1>; > }; > > - memory-controller@7000f400 { > + emc: memory-controller@7000f400 { > compatible = "nvidia,tegra30-emc"; > reg = <0x7000f400 0x400>; > interrupts = ; > clocks = <&tegra_car TEGRA30_CLK_EMC>; > > nvidia,memory-controller = <&mc>; > + No need for blank line. Best regards, Krzysztof > + #interconnect-cells = <0>; > }; > > fuse@7000f800 { > -- > 2.27.0 >