From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB41DC388F9 for ; Tue, 27 Oct 2020 19:39:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9344622275 for ; Tue, 27 Oct 2020 19:39:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603827576; bh=TqdeKbdqomt0pCdLikA/s/iCEfGiwOdKuyQw8BO6JOs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=dG/bIKiKgwkFn12rCblgj9e1xGSKeOvY4YyFlttoAd4OmVHxy3kNLTWiJBJmUwDrg GtD2AQZZtAKMSFvJZ2kuI5vSpHKVOcZFbnlwMW/DlVlq1Z+0WKZAC7vEGv+KS2uHXp kWI31UOBO6ubVGMiUFCCxVSXAZs1y+xIqDhLpZcg= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1762974AbgJ0Tjg convert rfc822-to-8bit (ORCPT ); Tue, 27 Oct 2020 15:39:36 -0400 Received: from mail-ed1-f68.google.com ([209.85.208.68]:37830 "EHLO mail-ed1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2504405AbgJ0Tjf (ORCPT ); Tue, 27 Oct 2020 15:39:35 -0400 Received: by mail-ed1-f68.google.com with SMTP id o18so2697061edq.4; Tue, 27 Oct 2020 12:39:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to; bh=prGqBiI5JimrXFF/vzXUDQaJ2EGlRDSeqqtNy7sjrCk=; b=eeR7ZZa3mX1J7wzslIN5qYkm+IQGhYbwJeOmzoTdhUPcL86D23ES7Jl5HoyCXGruDH KTLluNLroz3oyiWpKcmD4dzPWoGbfnHGdbbhXlBwN+9m1/dDEacXhT9P97iQ0CLzb0Sc fVzvHsbz+8fRmGrr/XFkCXGdFvEaA0N74CbVK+qmZQXBFh9krF5qDFV2PsPhRU6mZrR8 9ldQtTdh7mhiFABYLipfG6XGZxdK/PbDwlF7mYu6ANQIlgQSWeIl+vBFDvfFIcNtCXhG 7TkJD2+HMG50DA1gbOBxIVkSJTtEHoOpele95FXOm1rvC86K8M+1675sqGa+zdawEufW JWiQ== X-Gm-Message-State: AOAM531T+qFshkMml7G943NSB/MjydGTj0s1rC7pkm4WIbrnXzhxi6hE SnCkcDpDho/Da1wTAEM5lDc= X-Google-Smtp-Source: ABdhPJx/SLYaSJuvkdADGSTZROEQyUbm34KcNB5Cvm3aHaUVFHZ7v9Fg+sHR2VzYjZ1cuP6eGnu2Ow== X-Received: by 2002:a50:d0d0:: with SMTP id g16mr3879489edf.18.1603827573664; Tue, 27 Oct 2020 12:39:33 -0700 (PDT) Received: from kozik-lap ([194.230.155.184]) by smtp.googlemail.com with ESMTPSA id n22sm1534573edr.11.2020.10.27.12.39.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2020 12:39:32 -0700 (PDT) Date: Tue, 27 Oct 2020 20:39:30 +0100 From: Krzysztof Kozlowski To: Dmitry Osipenko Cc: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: Re: [PATCH v6 09/52] dt-bindings: memory: tegra30: mc: Document new interconnect property Message-ID: <20201027193930.GC140636@kozik-lap> References: <20201025221735.3062-1-digetx@gmail.com> <20201025221735.3062-10-digetx@gmail.com> <20201027090550.GI4244@kozik-lap> <7770b89e-f30b-3bfd-1e21-8ebbe905efcd@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8BIT In-Reply-To: <7770b89e-f30b-3bfd-1e21-8ebbe905efcd@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Oct 27, 2020 at 10:18:35PM +0300, Dmitry Osipenko wrote: > 27.10.2020 12:05, Krzysztof Kozlowski пишет: > > On Mon, Oct 26, 2020 at 01:16:52AM +0300, Dmitry Osipenko wrote: > >> Memory controller is interconnected with memory clients and with the > >> External Memory Controller. Document new interconnect property which > >> turns memory controller into interconnect provider. > >> > >> Acked-by: Rob Herring > >> Signed-off-by: Dmitry Osipenko > >> --- > >> .../bindings/memory-controllers/nvidia,tegra30-mc.yaml | 5 +++++ > >> 1 file changed, 5 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml > >> index 84fd57bcf0dc..5436e6d420bc 100644 > >> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml > >> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml > >> @@ -57,6 +57,9 @@ properties: > >> "#iommu-cells": > >> const: 1 > >> > >> + "#interconnect-cells": > >> + const: 1 > >> + > >> patternProperties: > >> "^emc-timings-[0-9]+$": > >> type: object > >> @@ -120,6 +123,7 @@ required: > >> - clock-names > >> - "#reset-cells" > >> - "#iommu-cells" > >> + - "#interconnect-cells" > > > > Rob, > > > > You were fine with adding a new required property which breaks all > > existing DTBs? > > This is a required property for the new bindings and optional for the > older. Does it really need to be made optional in the binding? Mhmm... that's an interesting point. I assumed that the bindings should reflect current status of the ABI, but I could imagine that you update the bindings while keeping the driver working with older DTBs. How do you actually track then the ABI? If incompatible change can be added to the bindings, later anyone anytime can also update the driver to enforce the bindings. To require such property. Best regards, Krzysztof > > > Were these bindings marked as unstable? The patchset does not even > > say/scream that it breaks the ABI, so this might be quite a surprise for > > someone... > > Please see tegra_mc_interconnect_setup() in "memory: tegra-mc: Add > interconnect framework" patch, which check presence of the new ICC DT > property.