From: Krzysztof Kozlowski <krzk@kernel.org>
To: Adam Ford <aford173@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org, aford@beaconembedded.com,
Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
NXP Linux Team <linux-imx@nxp.com>,
Andrey Smirnov <andrew.smirnov@gmail.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2 5/5] arm64: dts: imx8mn: Add GPU node
Date: Sun, 8 Nov 2020 19:48:13 +0100 [thread overview]
Message-ID: <20201108184813.GD7078@kozik-lap> (raw)
In-Reply-To: <20201107140026.1974312-5-aford173@gmail.com>
On Sat, Nov 07, 2020 at 08:00:25AM -0600, Adam Ford wrote:
> According to the documentation from NXP, the i.MX8M Nano has a
> Vivante GC7000 Ultra Lite as its GPU core.
>
> With this patch, the Etnaviv driver presents the GPU as:
> etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203
>
> The stock operating voltage for the i.MX8M Nano is .85V which means
> the GPU needs to run at 400MHz. For boards where the operating
> voltage is higher, this can be increased.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
> ---
> V2: Move into this series
> Update clocking description
>
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 25 +++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 5e4b6934de40..6e650ea422a7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -1008,6 +1008,31 @@ gpmi: nand-controller@33002000 {
> status = "disabled";
> };
>
> + gpu: gpu@38000000 {
> + compatible = "vivante,gc";
> + reg = <0x38000000 0x8000>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MN_CLK_GPU_AHB>,
> + <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
> + <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
> + <&clk IMX8MN_CLK_GPU_SHADER_DIV>;
> + clock-names = "reg", "bus", "core", "shader";
> + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>,
> + <&clk IMX8MN_CLK_GPU_SHADER_SRC>,
> + <&clk IMX8MN_CLK_GPU_AXI>,
> + <&clk IMX8MN_CLK_GPU_AHB>,
> + <&clk IMX8MN_GPU_PLL>,
> + <&clk IMX8MN_CLK_GPU_CORE_DIV>,
> + <&clk IMX8MN_CLK_GPU_SHADER_DIV>;
> + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
> + <&clk IMX8MN_GPU_PLL_OUT>,
> + <&clk IMX8MN_SYS_PLL1_800M>,
> + <&clk IMX8MN_SYS_PLL1_800M>;
> + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>,
> + <400000000>, <400000000>;
It would be nice to align indentation here to <0> above.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
prev parent reply other threads:[~2020-11-08 18:48 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-07 14:00 [PATCH V2 1/5] dt-bindings: add defines for i.MX8MN power domains Adam Ford
2020-11-07 14:00 ` [PATCH V2 2/5] soc: imx: gpcv2: add support " Adam Ford
2020-11-16 8:36 ` Shawn Guo
2020-11-07 14:00 ` [PATCH V2 3/5] arm64: dts: imx8mn: add GPC node and " Adam Ford
2020-11-08 18:45 ` Krzysztof Kozlowski
2020-11-07 14:00 ` [PATCH V2 4/5] arm64: dts: imx8mn: Add power-domain reference in USB controller Adam Ford
2020-11-08 18:45 ` Krzysztof Kozlowski
2020-11-07 14:00 ` [PATCH V2 5/5] arm64: dts: imx8mn: Add GPU node Adam Ford
2020-11-08 18:48 ` Krzysztof Kozlowski [this message]
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