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From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Georgi Djakov <georgi.djakov@linaro.org>
Cc: linux-pm@vger.kernel.org, mdtipton@codeaurora.org,
	devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	akashast@codeaurora.org
Subject: Re: [PATCH 2/3] interconnect: qcom: sdm845: Add the missing nodes for QUP
Date: Tue, 10 Nov 2020 22:37:03 -0600	[thread overview]
Message-ID: <20201111043703.GA173948@builder.lan> (raw)
In-Reply-To: <20201105135211.7160-2-georgi.djakov@linaro.org>

On Thu 05 Nov 07:52 CST 2020, Georgi Djakov wrote:

> The QUP nodes are currently defined just as entries in the topology,
> but they are not referenced by any of the NoCs. Let's fix this and
> "attach" them to their NoCs, so that the QUP drivers are able to use
> them as path endpoints and scale their bandwidth.
> 
> This is based on the information from the downstream msm-4.9 kernel.
> 
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>


Georgi, would you mind if I take the series through my tree, to avoid
conflicts in sdm845.dtsi?

Regards,
Bjorn

> ---
>  drivers/interconnect/qcom/sdm845.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c
> index 5304aea3b058..366870150cbd 100644
> --- a/drivers/interconnect/qcom/sdm845.c
> +++ b/drivers/interconnect/qcom/sdm845.c
> @@ -177,6 +177,7 @@ DEFINE_QBCM(bcm_sn15, "SN15", false, &qnm_memnoc);
>  
>  static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
>  	&bcm_sn9,
> +	&bcm_qup0,
>  };
>  
>  static struct qcom_icc_node *aggre1_noc_nodes[] = {
> @@ -190,6 +191,7 @@ static struct qcom_icc_node *aggre1_noc_nodes[] = {
>  	[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
>  	[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
>  	[SLAVE_ANOC_PCIE_A1NOC_SNOC] = &qns_pcie_a1noc_snoc,
> +	[MASTER_QUP_1] = &qhm_qup1,
>  };
>  
>  static const struct qcom_icc_desc sdm845_aggre1_noc = {
> @@ -218,6 +220,7 @@ static struct qcom_icc_node *aggre2_noc_nodes[] = {
>  	[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
>  	[SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc,
>  	[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
> +	[MASTER_QUP_2] = &qhm_qup2,
>  };
>  
>  static const struct qcom_icc_desc sdm845_aggre2_noc = {

  reply	other threads:[~2020-11-11  4:37 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-05 13:52 [PATCH 1/3] dt-bindings: interconnect: sdm845: Add IDs for the QUP ports Georgi Djakov
2020-11-05 13:52 ` [PATCH 2/3] interconnect: qcom: sdm845: Add the missing nodes for QUP Georgi Djakov
2020-11-11  4:37   ` Bjorn Andersson [this message]
2020-11-13 12:00     ` Georgi Djakov
2020-11-05 13:52 ` [PATCH 3/3] arm64: dts: sdm845: Add interconnect properties " Georgi Djakov
2020-11-09 20:02 ` [PATCH 1/3] dt-bindings: interconnect: sdm845: Add IDs for the QUP ports Rob Herring
2020-11-11  4:37 ` Bjorn Andersson

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