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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id v21sm3013136ota.78.2020.11.14.17.17.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Nov 2020 17:17:13 -0800 (PST) Date: Sat, 14 Nov 2020 19:17:11 -0600 From: Bjorn Andersson To: Vinod Koul Cc: Manivannan Sadhasivam , sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Naveen Yadav Subject: Re: [PATCH v2 2/4] clk: qcom: Add SDX55 GCC support Message-ID: <20201115011711.GI332990@builder.lan> References: <20201105104817.15715-1-manivannan.sadhasivam@linaro.org> <20201105104817.15715-3-manivannan.sadhasivam@linaro.org> <20201106093819.GE2621@vkoul-mobl> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20201106093819.GE2621@vkoul-mobl> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri 06 Nov 03:38 CST 2020, Vinod Koul wrote: > On 05-11-20, 16:18, Manivannan Sadhasivam wrote: > > From: Naveen Yadav > > > > Add Global Clock Controller (GCC) support for SDX55 SoCs from Qualcomm. > > > > Signed-off-by: Naveen Yadav > > [mani: converted to parent_data, commented critical clocks, cleanups] > > Signed-off-by: Manivannan Sadhasivam > > --- > > drivers/clk/qcom/Kconfig | 7 + > > drivers/clk/qcom/Makefile | 1 + > > drivers/clk/qcom/gcc-sdx55.c | 1626 ++++++++++++++++++++++++++++++++++ > > 3 files changed, 1634 insertions(+) > > create mode 100644 drivers/clk/qcom/gcc-sdx55.c > > > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > > index 3a965bd326d5..7897a3947e6d 100644 > > --- a/drivers/clk/qcom/Kconfig > > +++ b/drivers/clk/qcom/Kconfig > > @@ -413,6 +413,13 @@ config SDM_LPASSCC_845 > > Say Y if you want to use the LPASS branch clocks of the LPASS clock > > controller to reset the LPASS subsystem. > > > > +config SDX_GCC_55 > > + tristate "SDX55 Global Clock Controller" > > + help > > + Support for the global clock controller on SDX55 devices. > > + Say Y if you want to use peripheral devices such as UART, > > + SPI, I2C, USB, SD/UFS, PCIe etc. > > + > > config SM_DISPCC_8250 > > tristate "SM8150 and SM8250 Display Clock Controller" > > depends on SM_GCC_8150 || SM_GCC_8250 > > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > > index 11ae86febe87..886b877e70c7 100644 > > --- a/drivers/clk/qcom/Makefile > > +++ b/drivers/clk/qcom/Makefile > > @@ -64,6 +64,7 @@ obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o > > obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o > > obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o > > obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o > > +obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o > > obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o > > obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o > > obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o > > diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c > > new file mode 100644 > > index 000000000000..bf114165e24b > > --- /dev/null > > +++ b/drivers/clk/qcom/gcc-sdx55.c > > @@ -0,0 +1,1626 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > +/* > > + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. > > + * Copyright (c) 2020, Linaro Ltd. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > + > > +#include > > + > > +#include "common.h" > > +#include "clk-alpha-pll.h" > > +#include "clk-branch.h" > > +#include "clk-pll.h" > > +#include "clk-rcg.h" > > +#include "clk-regmap.h" > > +#include "reset.h" > > + > > +enum { > > + P_BI_TCXO, > > + P_CORE_BI_PLL_TEST_SE, > > This is for test and we removed this for upstream, so can you do that as > well (not parent will decrease for clks below) > We have several other platforms that includes the bi_pll_test clock - and it's there in the hardware, so I think we should just keep it. Is it causing any issues? Regards, Bjorn > With that updated: > > Reviewed-by: Vinod Koul > > -- > ~Vinod