* Re: [PATCH 3/6] dt-bindings: add bindings for polarfire soc mailbox
2020-11-19 17:04 [PATCH 3/6] dt-bindings: add bindings for polarfire soc mailbox conor.dooley
@ 2020-11-20 0:14 ` Damien Le Moal
2020-11-30 13:17 ` Conor.Dooley
2020-11-20 20:49 ` Rob Herring
2020-11-20 20:52 ` Rob Herring
2 siblings, 1 reply; 5+ messages in thread
From: Damien Le Moal @ 2020-11-20 0:14 UTC (permalink / raw)
To: conor.dooley@microchip.com, robh+dt@kernel.org,
jassisinghbrar@gmail.com, aou@eecs.berkeley.edu,
paul.walmsley@sifive.com, palmer@dabbelt.com,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org
Cc: cyril.jean@microchip.com, david.abdurachmanov@gmail.com,
daire.mcnamara@microchip.com, Anup Patel, Atish Patra,
lewis.hanly@microchip.com
On 2020/11/20 2:05, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the MSS system controller mailbox on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../mailbox/microchip,mpfs-mailbox.yaml | 46 +++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
>
> diff --git a/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
> new file mode 100644
> index 000000000000..5d6ccaa13dc2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Microchip MPFS mss mailbox controller
> +
> +maintainers:
> + - Conor Dooley <conor.dooley@microchip.com>
> +
> +properties:
> + compatible:
> + const: microchip,polarfire-soc-mailbox # PolarFire
> +
> + reg:
> + items:
> + - description: mailbox data registers
> + - description: mailbox int registers
> + maxItems: 2
> +
> + interrupts:
> + maxItems: 1
> +
> + "#mbox-cells":
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupt-parent
This one is not listed as a property above.
Did you run "make dt_binding_check" ?
> + - interrupts
> + - "#mbox-cells"
> +
> +unevaluatedProperties: false
> +additionalProperties: false
> +
> +examples:
> + - |
> + mailbox@37020000 {
> + compatible = "microchip,polarfire-soc-mailbox";
> + reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>;
> + interrupt-parent = <&L1>;
> + interrupts = <96>;
> + #mbox-cells = <1>;
> + };
>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH 3/6] dt-bindings: add bindings for polarfire soc mailbox
2020-11-20 0:14 ` Damien Le Moal
@ 2020-11-30 13:17 ` Conor.Dooley
0 siblings, 0 replies; 5+ messages in thread
From: Conor.Dooley @ 2020-11-30 13:17 UTC (permalink / raw)
To: Damien.LeMoal, robh+dt, jassisinghbrar, aou, paul.walmsley,
palmer, devicetree, linux-riscv
Cc: Cyril.Jean, david.abdurachmanov, Daire.McNamara, Anup.Patel,
Atish.Patra, Lewis.Hanly
On 20/11/2020 00:14, Damien Le Moal wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 2020/11/20 2:05, conor.dooley@microchip.com wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> Add device tree bindings for the MSS system controller mailbox on
>> the Microchip PolarFire SoC.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> .../mailbox/microchip,mpfs-mailbox.yaml | 46 +++++++++++++++++++
>> 1 file changed, 46 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
>> new file mode 100644
>> index 000000000000..5d6ccaa13dc2
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
>> @@ -0,0 +1,46 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: Microchip MPFS mss mailbox controller
>> +
>> +maintainers:
>> + - Conor Dooley <conor.dooley@microchip.com>
>> +
>> +properties:
>> + compatible:
>> + const: microchip,polarfire-soc-mailbox # PolarFire
>> +
>> + reg:
>> + items:
>> + - description: mailbox data registers
>> + - description: mailbox int registers
>> + maxItems: 2
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + "#mbox-cells":
>> + const: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - interrupt-parent
> This one is not listed as a property above.
> Did you run "make dt_binding_check" ?
I did, causes a fail if it is listed as a property. I'm going to remove it entirely in V2.
>> + - interrupts
>> + - "#mbox-cells"
>> +
>> +unevaluatedProperties: false
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + mailbox@37020000 {
>> + compatible = "microchip,polarfire-soc-mailbox";
>> + reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>;
>> + interrupt-parent = <&L1>;
>> + interrupts = <96>;
>> + #mbox-cells = <1>;
>> + };
>>
>
> --
> Damien Le Moal
> Western Digital Research
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 3/6] dt-bindings: add bindings for polarfire soc mailbox
2020-11-19 17:04 [PATCH 3/6] dt-bindings: add bindings for polarfire soc mailbox conor.dooley
2020-11-20 0:14 ` Damien Le Moal
@ 2020-11-20 20:49 ` Rob Herring
2020-11-20 20:52 ` Rob Herring
2 siblings, 0 replies; 5+ messages in thread
From: Rob Herring @ 2020-11-20 20:49 UTC (permalink / raw)
To: conor.dooley
Cc: jassisinghbrar, devicetree, aou, linux-riscv, anup.patel,
david.abdurachmanov, palmer, daire.mcnamara, lewis.hanly,
atish.patra, robh+dt, paul.walmsley, cyril.jean
On Thu, 19 Nov 2020 17:04:32 +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the MSS system controller mailbox on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../mailbox/microchip,mpfs-mailbox.yaml | 46 +++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.example.dt.yaml: example-0: mailbox@37020000:reg:0: [0, 922877952, 0, 4096] is too long
From schema: /usr/local/lib/python3.8/dist-packages/dtschema/schemas/reg.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.example.dt.yaml: example-0: mailbox@37020000:reg:1: [0, 536883596, 0, 64] is too long
From schema: /usr/local/lib/python3.8/dist-packages/dtschema/schemas/reg.yaml
See https://patchwork.ozlabs.org/patch/1403152
The base for the patch is generally the last rc1. Any dependencies
should be noted.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 3/6] dt-bindings: add bindings for polarfire soc mailbox
2020-11-19 17:04 [PATCH 3/6] dt-bindings: add bindings for polarfire soc mailbox conor.dooley
2020-11-20 0:14 ` Damien Le Moal
2020-11-20 20:49 ` Rob Herring
@ 2020-11-20 20:52 ` Rob Herring
2 siblings, 0 replies; 5+ messages in thread
From: Rob Herring @ 2020-11-20 20:52 UTC (permalink / raw)
To: conor.dooley
Cc: jassisinghbrar, aou, paul.walmsley, palmer, devicetree,
linux-riscv, lewis.hanly, cyril.jean, daire.mcnamara, atish.patra,
anup.patel, david.abdurachmanov
On Thu, Nov 19, 2020 at 05:04:32PM +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the MSS system controller mailbox on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../mailbox/microchip,mpfs-mailbox.yaml | 46 +++++++++++++++++++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
>
> diff --git a/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
> new file mode 100644
> index 000000000000..5d6ccaa13dc2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Microchip MPFS mss mailbox controller
> +
> +maintainers:
> + - Conor Dooley <conor.dooley@microchip.com>
> +
> +properties:
> + compatible:
> + const: microchip,polarfire-soc-mailbox # PolarFire
Comment is redundant.
> +
> + reg:
> + items:
> + - description: mailbox data registers
> + - description: mailbox int registers
> + maxItems: 2
maxItems is implied by size of 'items'.
> +
> + interrupts:
> + maxItems: 1
> +
> + "#mbox-cells":
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupt-parent
> + - interrupts
> + - "#mbox-cells"
> +
> +unevaluatedProperties: false
> +additionalProperties: false
Only need one and in this case additionalProperties.
> +
> +examples:
> + - |
> + mailbox@37020000 {
> + compatible = "microchip,polarfire-soc-mailbox";
> + reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>;
> + interrupt-parent = <&L1>;
> + interrupts = <96>;
> + #mbox-cells = <1>;
> + };
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread