* [PATCH 1/2] bindings: perf: imx-ddr: add compatible string
2020-11-28 5:30 [PATCH 0/2] perf/imx_ddr: Add sysfs identifier file Joakim Zhang
@ 2020-11-28 5:30 ` Joakim Zhang
2020-11-28 5:30 ` [PATCH 2/2] perf/imx_ddr: Add system PMU identifier for userspace Joakim Zhang
1 sibling, 0 replies; 4+ messages in thread
From: Joakim Zhang @ 2020-11-28 5:30 UTC (permalink / raw)
To: will, john.garry, robh+dt; +Cc: devicetree, LnxRevLi, frank.li
Add extra compabile string to support driver.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml
index 5aad9f4e0b2a..80a92385367e 100644
--- a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml
+++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml
@@ -15,6 +15,9 @@ properties:
- enum:
- fsl,imx8-ddr-pmu
- fsl,imx8m-ddr-pmu
+ - fsl,imx8mq-ddr-pmu
+ - fsl,imx8mm-ddr-pmu
+ - fsl,imx8mn-ddr-pmu
- fsl,imx8mp-ddr-pmu
- items:
- enum:
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 2/2] perf/imx_ddr: Add system PMU identifier for userspace
2020-11-28 5:30 [PATCH 0/2] perf/imx_ddr: Add sysfs identifier file Joakim Zhang
2020-11-28 5:30 ` [PATCH 1/2] bindings: perf: imx-ddr: add compatible string Joakim Zhang
@ 2020-11-28 5:30 ` Joakim Zhang
1 sibling, 0 replies; 4+ messages in thread
From: Joakim Zhang @ 2020-11-28 5:30 UTC (permalink / raw)
To: will, john.garry, robh+dt; +Cc: devicetree, LnxRevLi, frank.li
The DDR Perf for i.MX8 is a system PMU whose AXI ID would different from
SoC to SoC. Need expose system PMU identifier for userspace which refer
to /sys/bus/event_source/devices/<PMU DEVICE>/identifier.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
drivers/perf/fsl_imx8_ddr_perf.c | 42 ++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
index 4f063fb1c6b4..3517d2fb1469 100644
--- a/drivers/perf/fsl_imx8_ddr_perf.c
+++ b/drivers/perf/fsl_imx8_ddr_perf.c
@@ -50,6 +50,7 @@ static DEFINE_IDA(ddr_ida);
struct fsl_ddr_devtype_data {
unsigned int quirks; /* quirks needed for different DDR Perf core */
+ const char *identifier; /* system PMU identifier for userspace */
};
static const struct fsl_ddr_devtype_data imx8_devtype_data;
@@ -58,13 +59,32 @@ static const struct fsl_ddr_devtype_data imx8m_devtype_data = {
.quirks = DDR_CAP_AXI_ID_FILTER,
};
+static const struct fsl_ddr_devtype_data imx8mq_devtype_data = {
+ .quirks = DDR_CAP_AXI_ID_FILTER,
+ .identifier = "i.MX8MQ",
+};
+
+static const struct fsl_ddr_devtype_data imx8mm_devtype_data = {
+ .quirks = DDR_CAP_AXI_ID_FILTER,
+ .identifier = "i.MX8MM",
+};
+
+static const struct fsl_ddr_devtype_data imx8mn_devtype_data = {
+ .quirks = DDR_CAP_AXI_ID_FILTER,
+ .identifier = "i.MX8MN",
+};
+
static const struct fsl_ddr_devtype_data imx8mp_devtype_data = {
.quirks = DDR_CAP_AXI_ID_FILTER_ENHANCED,
+ .identifier = "i.MX8MP",
};
static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
{ .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
{ .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
+ { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
+ { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
+ { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
{ .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
{ /* sentinel */ }
};
@@ -84,6 +104,27 @@ struct ddr_pmu {
int id;
};
+static ssize_t ddr_perf_identifier_show(struct device *dev,
+ struct device_attribute *attr,
+ char *page)
+{
+ struct ddr_pmu *pmu = dev_get_drvdata(dev);
+
+ return sprintf(page, "%s\n", pmu->devtype_data->identifier);
+}
+
+static struct device_attribute ddr_perf_identifier_attr =
+ __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL);
+
+static struct attribute *ddr_perf_identifier_attrs[] = {
+ &ddr_perf_identifier_attr.attr,
+ NULL,
+};
+
+static struct attribute_group ddr_perf_identifier_attr_group = {
+ .attrs = ddr_perf_identifier_attrs,
+};
+
enum ddr_perf_filter_capabilities {
PERF_CAP_AXI_ID_FILTER = 0,
PERF_CAP_AXI_ID_FILTER_ENHANCED,
@@ -237,6 +278,7 @@ static const struct attribute_group *attr_groups[] = {
&ddr_perf_format_attr_group,
&ddr_perf_cpumask_attr_group,
&ddr_perf_filter_cap_attr_group,
+ &ddr_perf_identifier_attr_group,
NULL,
};
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread