From: <conor.dooley@microchip.com>
To: <robh+dt@kernel.org>, <damien.lemoal@wdc.com>,
<jassisinghbrar@gmail.com>, <aou@eecs.berkeley.edu>,
<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>
Cc: <lewis.hanly@microchip.com>, <cyril.jean@microchip.com>,
<daire.mcnamara@microchip.com>, <atish.patra@wdc.com>,
<anup.patel@wdc.com>, <david.abdurachmanov@gmail.com>,
Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v2 5/5] MAINTAINERS: add microchip polarfire soc support
Date: Tue, 1 Dec 2020 11:03:16 +0000 [thread overview]
Message-ID: <20201201110316.28656-1-conor.dooley@microchip.com> (raw)
From: Conor Dooley <conor.dooley@microchip.com>
Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC
directory
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2daa6ee673f7..2241bdac4816 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14989,6 +14989,15 @@ F: arch/riscv/
N: riscv
K: riscv
+RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
+M: Lewis Hanly <lewis.hanly@microchip.com>
+M: Cyril Jean <cyril.jean@microchip.com>
+L: linux-riscv@lists.infradead.org
+S: Supported
+F: drivers/mailbox/mailbox-mpfs.c
+F: drivers/soc/microchip/
+F: include/soc/microchip/mpfs.h
+
RNBD BLOCK DRIVERS
M: Danil Kipnis <danil.kipnis@cloud.ionos.com>
M: Jack Wang <jinpu.wang@cloud.ionos.com>
--
2.17.1
next reply other threads:[~2020-12-01 11:05 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-01 11:03 conor.dooley [this message]
2020-12-01 18:06 ` [PATCH v2 5/5] MAINTAINERS: add microchip polarfire soc support Atish Patra
2020-12-02 9:13 ` Conor.Dooley
2020-12-02 18:44 ` Atish Patra
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