From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Rob Herring <robh+dt@kernel.org>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: [PATCH 3/3] arm64: dts: qcom: sm8250: add ddrss_sf_tbu clock to PCIe device nodes
Date: Tue, 8 Dec 2020 03:46:13 +0300 [thread overview]
Message-ID: <20201208004613.1472278-4-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20201208004613.1472278-1-dmitry.baryshkov@linaro.org>
On SM8250 additional clock is required for PCIe devices to access NOC.
Add this clock to PCIe devices nodes.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index deed186b1a84..4a6e11e78b35 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -1345,14 +1345,16 @@ pcie0: pci@1c00000 {
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
- <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
- "tbu";
+ "tbu",
+ "ddrss_sf_tbu";
iommus = <&apps_smmu 0x1c00 0x7f>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
@@ -1437,7 +1439,8 @@ pcie1: pci@1c08000 {
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_WIGIG_CLKREF_EN>,
- <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
clock-names = "pipe",
"aux",
"cfg",
@@ -1445,7 +1448,8 @@ pcie1: pci@1c08000 {
"bus_slave",
"slave_q2a",
"ref",
- "tbu";
+ "tbu",
+ "ddrss_sf_tbu";
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
assigned-clock-rates = <19200000>;
@@ -1535,7 +1539,8 @@ pcie2: pci@1c10000 {
<&gcc GCC_PCIE_2_SLV_AXI_CLK>,
<&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_MDM_CLKREF_EN>,
- <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
clock-names = "pipe",
"aux",
"cfg",
@@ -1543,7 +1548,8 @@ pcie2: pci@1c10000 {
"bus_slave",
"slave_q2a",
"ref",
- "tbu";
+ "tbu",
+ "ddrss_sf_tbu";
assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
assigned-clock-rates = <19200000>;
--
2.29.2
prev parent reply other threads:[~2020-12-08 0:47 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-08 0:46 [PATCH 0/3] Fixup PCIe support on sm8250 Dmitry Baryshkov
2020-12-08 0:46 ` [PATCH 1/3] dt-bindings: pci: qcom: Document ddrss_sf_tbu clock for sm8250 Dmitry Baryshkov
2020-12-10 3:55 ` Rob Herring
2020-12-08 0:46 ` [PATCH 2/3] PCI: qcom: add support for ddrss_sf_tbu clock Dmitry Baryshkov
2020-12-08 0:46 ` Dmitry Baryshkov [this message]
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