From: Rob Herring <robh@kernel.org>
To: Yash Shah <yash.shah@sifive.com>
Cc: anup@brainfault.org, bp@suse.de, paul.walmsley@sifive.com,
sagar.kadam@sifive.com, sachin.ghadi@sifive.com,
devicetree@vger.kernel.org, palmer@dabbelt.com,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
robh+dt@kernel.org, aou@eecs.berkeley.edu,
Jonathan.Cameron@huawei.com, sam@ravnborg.org, wsa@kernel.org
Subject: Re: [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740
Date: Thu, 10 Dec 2020 21:46:44 -0600 [thread overview]
Message-ID: <20201211034644.GA3602957@robh.at.kernel.org> (raw)
In-Reply-To: <1607596083-81480-2-git-send-email-yash.shah@sifive.com>
On Thu, 10 Dec 2020 15:58:02 +0530, Yash Shah wrote:
> The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
> compared to 3 in FU540. Update the DT documentation accordingly with
> "compatible" and "interrupt" property changes.
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> ---
> .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++++++++++++++++++---
> 1 file changed, 30 insertions(+), 4 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2020-12-11 3:48 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-10 10:28 [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC Yash Shah
2020-12-10 10:28 ` [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740 Yash Shah
2020-12-11 1:55 ` Palmer Dabbelt
2020-12-11 3:46 ` Rob Herring [this message]
2020-12-10 10:28 ` [PATCH v3 2/2] RISC-V: sifive_l2_cache: Update L2 cache driver to support " Yash Shah
2021-01-08 1:36 ` [PATCH v3 0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC Palmer Dabbelt
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