From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.7 required=3.0 tests=BAYES_00, DATE_IN_FUTURE_24_48,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1178AC3526C for ; Fri, 11 Dec 2020 12:01:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DBFE223E21 for ; Fri, 11 Dec 2020 12:01:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405871AbgLKMAf (ORCPT ); Fri, 11 Dec 2020 07:00:35 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:9431 "EHLO szxga06-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727092AbgLKL7w (ORCPT ); Fri, 11 Dec 2020 06:59:52 -0500 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4Csq7N73dHzhqWt; Fri, 11 Dec 2020 19:58:40 +0800 (CST) Received: from huawei.com (10.151.151.249) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.487.0; Fri, 11 Dec 2020 19:59:01 +0800 From: Dongjiu Geng To: , , , , , , , , , , Subject: [PATCH RESEND v6 3/4] dt: bindings: dma: Add DT bindings for HiSilicon Hiedma Controller Date: Sat, 12 Dec 2020 13:11:14 +0000 Message-ID: <20201212131115.569-4-gengdongjiu@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201212131115.569-1-gengdongjiu@huawei.com> References: <20201212131115.569-1-gengdongjiu@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.151.151.249] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Hiedma Controller v310 Provides eight DMA channels, each channel can be configured for one-way transfer. The data can be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This documentation describes DT bindings of this controller. Signed-off-by: Dongjiu Geng --- .../bindings/dma/hisilicon,hiedmacv310.yaml | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml diff --git a/Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml b/Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml new file mode 100644 index 000000000000..f57703fbbe7b --- /dev/null +++ b/Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/hisilicon,hiedmacv310.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Hiedma Controller v310 Device Tree Bindings + +description: | + These bindings describe the DMA engine included in the HiSilicon Hiedma + Controller v310 Device. + +maintainers: + - Dongjiu Geng + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + "#dma-cells": + const: 2 + + compatible: + const: hisilicon,hiedmacv310 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + hisi,misc-control: + $ref: /schemas/types.yaml#definitions/phandle-array + description: phandle pointing to the misc controller provider node and base register. + + clocks: + items: + - description: apb clock + - description: axi clock + + clock-names: + items: + - const: apb_pclk + - const: axi_aclk + + resets: + description: phandle pointing to the dma reset controller provider node. + + reset-names: + items: + - const: dma-reset + + dma-requests: + maximum: 32 + + dma-channels: + maximum: 8 + + +required: + - "#dma-cells" + - compatible + - hisi,misc-control + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - dma-requests + - dma-channels + +additionalProperties: false + +examples: + - | + #include + #include + + dma: dma-controller@10040000 { + compatible = "hisilicon,hiedmacv310"; + reg = <0x10040000 0x1000>; + hisi,misc-control = <&misc_ctrl 0x144>; + interrupts = <0 82 4>; + clocks = <&clock HI3559AV100_EDMAC1_CLK>, <&clock HI3559AV100_EDMAC1_AXICLK>; + clock-names = "apb_pclk", "axi_aclk"; + resets = <&clock 0x16c 7>; + reset-names = "dma-reset"; + dma-requests = <32>; + dma-channels = <8>; + #dma-cells = <2>; + }; + +... -- 2.17.1