From: "Guido Günther" <guido.gunther@puri.sm>
To: Liu Ying <victor.liu@nxp.com>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org, kishon@ti.com,
vkoul@kernel.org, robh+dt@kernel.org, a.hajda@samsung.com,
narmstrong@baylibre.com, Laurent.pinchart@ideasonboard.com,
jonas@kwiboo.se, jernej.skrabec@siol.net, airlied@linux.ie,
daniel@ffwll.ch, shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
robert.chiras@nxp.com, martin.kepplinger@puri.sm
Subject: Re: [PATCH 1/4] drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_enable()
Date: Tue, 15 Dec 2020 09:30:19 +0100 [thread overview]
Message-ID: <20201215083019.GA11854@bogon.m.sigxcpu.org> (raw)
In-Reply-To: <20201208090457.GB20575@bogon.m.sigxcpu.org>
Hi,
On Tue, Dec 08, 2020 at 10:04:57AM +0100, Guido Günther wrote:
> Hi,
> On Fri, Dec 04, 2020 at 03:33:41PM +0800, Liu Ying wrote:
> > The Northwest Logic MIPI DSI host controller embedded in i.MX8qxp
> > works with a Mixel MIPI DPHY + LVDS PHY combo to support either
> > a MIPI DSI display or a LVDS display. So, this patch calls
> > phy_set_mode() from nwl_dsi_enable() to set PHY mode to MIPI DPHY
> > explicitly.
Should i pull this patch in via drm-misc-next or is the whole series
supposed to go via the phy tree?
Cheers,
-- Guido
> >
> > Cc: Guido Günther <agx@sigxcpu.org>
> > Cc: Robert Chiras <robert.chiras@nxp.com>
> > Cc: Martin Kepplinger <martin.kepplinger@puri.sm>
> > Cc: Andrzej Hajda <a.hajda@samsung.com>
> > Cc: Neil Armstrong <narmstrong@baylibre.com>
> > Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
> > Cc: Jonas Karlman <jonas@kwiboo.se>
> > Cc: Jernej Skrabec <jernej.skrabec@siol.net>
> > Cc: David Airlie <airlied@linux.ie>
> > Cc: Daniel Vetter <daniel@ffwll.ch>
> > Cc: NXP Linux Team <linux-imx@nxp.com>
> > Signed-off-by: Liu Ying <victor.liu@nxp.com>
> > ---
> > drivers/gpu/drm/bridge/nwl-dsi.c | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
> > index 66b6740..be6bfc5 100644
> > --- a/drivers/gpu/drm/bridge/nwl-dsi.c
> > +++ b/drivers/gpu/drm/bridge/nwl-dsi.c
> > @@ -678,6 +678,12 @@ static int nwl_dsi_enable(struct nwl_dsi *dsi)
> > return ret;
> > }
> >
> > + ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
> > + if (ret < 0) {
> > + DRM_DEV_ERROR(dev, "Failed to set DSI phy mode: %d\n", ret);
> > + goto uninit_phy;
> > + }
> > +
> > ret = phy_configure(dsi->phy, phy_cfg);
> > if (ret < 0) {
> > DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret);
>
> Reviewed-by: Guido Günther <agx@sigxcpu.org>
> -- Guido
>
> > --
> > 2.7.4
> >
>
>
next prev parent reply other threads:[~2020-12-15 8:31 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-04 7:33 [PATCH 0/4] phy: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support Liu Ying
2020-12-04 7:33 ` [PATCH 1/4] drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_enable() Liu Ying
2020-12-08 9:04 ` Guido Günther
2020-12-15 8:30 ` Guido Günther [this message]
2020-12-04 7:33 ` [PATCH 2/4] phy: Add LVDS configuration options Liu Ying
2020-12-08 12:38 ` Laurent Pinchart
2020-12-09 1:20 ` Liu Ying
2020-12-04 7:33 ` [PATCH 3/4] dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for i.MX8qxp Liu Ying
2020-12-08 9:07 ` Guido Günther
2020-12-08 9:46 ` Liu Ying
2020-12-04 7:33 ` [PATCH 4/4] phy: freescale: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support Liu Ying
2020-12-08 9:24 ` Guido Günther
2020-12-08 10:03 ` Liu Ying
2020-12-10 7:14 ` Guido Günther
2020-12-10 8:56 ` Liu Ying
2020-12-08 9:02 ` [PATCH 0/4] phy: " Guido Günther
2020-12-08 9:40 ` Liu Ying
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