From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4308FC4361B for ; Thu, 17 Dec 2020 11:21:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 039792389E for ; Thu, 17 Dec 2020 11:21:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726998AbgLQLVd (ORCPT ); Thu, 17 Dec 2020 06:21:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726012AbgLQLVd (ORCPT ); Thu, 17 Dec 2020 06:21:33 -0500 Received: from leonov.paulk.fr (vpn-0-22.aquilenet.fr [IPv6:2a0c:e300:4:22::]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B38B0C0617A7; Thu, 17 Dec 2020 03:20:52 -0800 (PST) Received: from gagarine.paulk.fr (gagarine [192.168.1.127]) by leonov.paulk.fr (Postfix) with ESMTPS id 0F849C0139; Thu, 17 Dec 2020 12:20:50 +0100 (CET) Received: by gagarine.paulk.fr (Postfix, from userid 114) id 72AFEC1D22; Thu, 17 Dec 2020 12:20:49 +0100 (CET) Received: from localhost.localdomain (collins [192.168.1.129]) by gagarine.paulk.fr (Postfix) with ESMTP id 8BB44C18D2; Thu, 17 Dec 2020 12:20:36 +0100 (CET) From: Paul Kocialkowski To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Paul Kocialkowski Subject: [PATCH] ARM: dts: sun8i-v3s: Add PWM controller and pins definitions Date: Thu, 17 Dec 2020 12:20:31 +0100 Message-Id: <20201217112031.2243683-1-contact@paulk.fr> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This introduces definitions for the PWM controller found in the V3s, as well as associated pins. This fashion of the controller has two PWM outputs and is register-compatible with the A20. Both PWM outputs were tested on a Lichee Pi Zero with a simple transistor-LED setup. Signed-off-by: Paul Kocialkowski --- arch/arm/boot/dts/sun8i-v3s.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index a9f5795d4e57..34a4e638c762 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -398,6 +398,16 @@ spi0_pins: spi0-pins { pins = "PC0", "PC1", "PC2", "PC3"; function = "spi0"; }; + + pwm0_pin: pwm0-pin { + pins = "PB4"; + function = "pwm0"; + }; + + pwm1_pin: pwm1-pin { + pins = "PB5"; + function = "pwm1"; + }; }; timer@1c20c00 { @@ -416,6 +426,14 @@ wdt0: watchdog@1c20ca0 { clocks = <&osc24M>; }; + pwm: pwm@1c21400 { + compatible = "allwinner,sun7i-a20-pwm"; + reg = <0x01c21400 0xc>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + lradc: lradc@1c22800 { compatible = "allwinner,sun4i-a10-lradc-keys"; reg = <0x01c22800 0x400>; -- 2.29.2