From: Eric Biggers <ebiggers@kernel.org>
To: linux-mmc@vger.kernel.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-fscrypt@vger.kernel.org,
Satya Tangirala <satyat@google.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Adrian Hunter <adrian.hunter@intel.com>,
Asutosh Das <asutoshd@codeaurora.org>,
Rob Herring <robh+dt@kernel.org>,
Neeraj Soni <neersoni@codeaurora.org>,
Barani Muthukumaran <bmuthuku@codeaurora.org>,
Peng Zhou <peng.zhou@mediatek.com>,
Stanley Chu <stanley.chu@mediatek.com>,
Konrad Dybcio <konradybcio@gmail.com>
Subject: [PATCH v4 8/9] arm64: dts: qcom: sdm630: add ICE registers and clocks
Date: Mon, 4 Jan 2021 10:45:41 -0800 [thread overview]
Message-ID: <20210104184542.4616-9-ebiggers@kernel.org> (raw)
In-Reply-To: <20210104184542.4616-1-ebiggers@kernel.org>
From: Eric Biggers <ebiggers@google.com>
Add the registers and clock for the Inline Crypto Engine (ICE) to the
device tree node for the sdhci-msm host controller on sdm630. This
allows sdhci-msm to support inline encryption on sdm630.
Signed-off-by: Eric Biggers <ebiggers@google.com>
---
arch/arm64/boot/dts/qcom/sdm630.dtsi | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index 37d5cc32f6b62..afb3d20c31fa0 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -808,8 +808,9 @@ spmi_bus: spmi@800f000 {
sdhc_1: sdhci@c0c4000 {
compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
reg = <0x0c0c4000 0x1000>,
- <0x0c0c5000 0x1000>;
- reg-names = "hc", "cqhci";
+ <0x0c0c5000 0x1000>,
+ <0x0c0c8000 0x8000>;
+ reg-names = "hc", "cqhci", "ice";
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
@@ -817,8 +818,9 @@ sdhc_1: sdhci@c0c4000 {
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
- <&xo_board>;
- clock-names = "core", "iface", "xo";
+ <&xo_board>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "core", "iface", "xo", "ice";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
--
2.30.0
next prev parent reply other threads:[~2021-01-04 18:49 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-04 18:45 [PATCH v4 0/9] eMMC inline encryption support Eric Biggers
2021-01-04 18:45 ` [PATCH v4 1/9] mmc: add basic support for inline encryption Eric Biggers
2021-01-15 9:22 ` Ulf Hansson
2021-01-15 17:56 ` Eric Biggers
2021-01-18 14:21 ` Ulf Hansson
2021-01-19 20:51 ` Eric Biggers
2021-01-21 7:45 ` Eric Biggers
2021-01-21 9:18 ` Eric Biggers
2021-01-21 13:08 ` Ulf Hansson
2021-01-04 18:45 ` [PATCH v4 2/9] mmc: cqhci: rename cqhci.c to cqhci-core.c Eric Biggers
2021-01-04 18:45 ` [PATCH v4 3/9] mmc: cqhci: initialize upper 64 bits of 128-bit task descriptors Eric Biggers
2021-01-04 18:45 ` [PATCH v4 4/9] mmc: cqhci: add support for inline encryption Eric Biggers
2021-01-04 18:45 ` [PATCH v4 5/9] mmc: cqhci: add cqhci_host_ops::program_key Eric Biggers
2021-01-04 18:45 ` [PATCH v4 6/9] firmware: qcom_scm: update comment for ICE-related functions Eric Biggers
2021-01-04 18:45 ` [PATCH v4 7/9] dt-bindings: mmc: sdhci-msm: add ICE registers and clock Eric Biggers
2021-01-04 18:45 ` Eric Biggers [this message]
2021-01-04 18:45 ` [PATCH v4 9/9] mmc: sdhci-msm: add Inline Crypto Engine support Eric Biggers
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