From: Joakim Zhang <qiangqing.zhang@nxp.com>
To: shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com
Cc: devicetree@vger.kernel.org, linux-imx@nxp.com
Subject: [PATCH V2 2/5] arm64: dts: imx8m: correct assigned clocks for FEC
Date: Sat, 16 Jan 2021 16:44:28 +0800 [thread overview]
Message-ID: <20210116084431.25851-3-qiangqing.zhang@nxp.com> (raw)
In-Reply-To: <20210116084431.25851-1-qiangqing.zhang@nxp.com>
CLK_ENET_TIMER assigned clocks twice, should be a typo, correct to
CLK_ENET_PHY_REF clock.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 7 ++++---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 7 ++++---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 7 ++++---
3 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 9bee6f1889a4..5af0e63b1db1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -915,11 +915,12 @@
assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
<&clk IMX8MM_CLK_ENET_TIMER>,
<&clk IMX8MM_CLK_ENET_REF>,
- <&clk IMX8MM_CLK_ENET_TIMER>;
+ <&clk IMX8MM_CLK_ENET_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
<&clk IMX8MM_SYS_PLL2_100M>,
- <&clk IMX8MM_SYS_PLL2_125M>;
- assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+ <&clk IMX8MM_SYS_PLL2_125M>,
+ <&clk IMX8MM_SYS_PLL2_50M>;
+ assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index fcf580816320..9dc52747a142 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -913,11 +913,12 @@
assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
<&clk IMX8MN_CLK_ENET_TIMER>,
<&clk IMX8MN_CLK_ENET_REF>,
- <&clk IMX8MN_CLK_ENET_TIMER>;
+ <&clk IMX8MN_CLK_ENET_PHY_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
<&clk IMX8MN_SYS_PLL2_100M>,
- <&clk IMX8MN_SYS_PLL2_125M>;
- assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+ <&clk IMX8MN_SYS_PLL2_125M>,
+ <&clk IMX8MN_SYS_PLL2_50M>;
+ assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 9401e92f1c84..ba32725ff28c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -768,11 +768,12 @@
assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
<&clk IMX8MP_CLK_ENET_TIMER>,
<&clk IMX8MP_CLK_ENET_REF>,
- <&clk IMX8MP_CLK_ENET_TIMER>;
+ <&clk IMX8MP_CLK_ENET_PHY_REF>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
- <&clk IMX8MP_SYS_PLL2_125M>;
- assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+ <&clk IMX8MP_SYS_PLL2_125M>,
+ <&clk IMX8MP_SYS_PLL2_50M>;
+ assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
status = "disabled";
--
2.17.1
next prev parent reply other threads:[~2021-01-16 8:46 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-16 8:44 [PATCH V2 0/5] patches for FEC Joakim Zhang
2021-01-16 8:44 ` [PATCH V2 1/5] ARM: dts: imx6: add wakeup support via magic packet Joakim Zhang
2021-01-16 8:44 ` Joakim Zhang [this message]
2021-01-16 8:44 ` [PATCH V2 3/5] arm64: dts: imx8mq: assign clock parents for FEC Joakim Zhang
2021-01-16 8:44 ` [PATCH V2 4/5] arm64: dts: imx8m: add mac address " Joakim Zhang
2021-01-16 8:44 ` [PATCH V2 5/5] arm64: dts: imx8m: add fsl,stop-mode property " Joakim Zhang
2021-01-18 9:40 ` [PATCH V2 0/5] patches " Shawn Guo
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