From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD692C433DB for ; Sat, 30 Jan 2021 18:12:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AD0C664E13 for ; Sat, 30 Jan 2021 18:12:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231903AbhA3SMd (ORCPT ); Sat, 30 Jan 2021 13:12:33 -0500 Received: from mail-out.m-online.net ([212.18.0.9]:50176 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231820AbhA3SMd (ORCPT ); Sat, 30 Jan 2021 13:12:33 -0500 Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 4DSj2P69GRz1qs38; Sat, 30 Jan 2021 19:11:25 +0100 (CET) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 4DSj2P5w3Tz1tYTW; Sat, 30 Jan 2021 19:11:25 +0100 (CET) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id QbQfprgeWiUm; Sat, 30 Jan 2021 19:11:24 +0100 (CET) X-Auth-Info: 75/lHBaT8xbCLaC9OrnnjV35XGPS4ICpUqxE9NR3rdM= Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Sat, 30 Jan 2021 19:11:24 +0100 (CET) From: Marek Vasut To: dri-devel@lists.freedesktop.org Cc: Marek Vasut , Rob Herring , Sam Ravnborg , devicetree@vger.kernel.org Subject: [PATCH 3/3] drm/panel: simple: Add Displaytech DT050TFT-PTS panel Date: Sat, 30 Jan 2021 19:11:14 +0100 Message-Id: <20210130181114.161515-3-marex@denx.de> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210130181114.161515-1-marex@denx.de> References: <20210130181114.161515-1-marex@denx.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the Displaytech DT050TFT-PTS 5.0" (800x480) color TFT LCD panel, connected over DPI. Timings are taken from the datasheet Rev 0.0. Signed-off-by: Marek Vasut Cc: dri-devel@lists.freedesktop.org Cc: Rob Herring Cc: Sam Ravnborg Cc: devicetree@vger.kernel.org --- drivers/gpu/drm/panel/panel-simple.c | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 204674fccd64..4e31fe04fe49 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -1625,6 +1625,36 @@ static const struct panel_desc dataimage_scf0700c48ggu18 = { .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, }; +static const struct display_timing displaytech_dt050tft_pts_timing = { + .pixelclock = { 30000000, 40000000, 50000000 }, + .hactive = { 800, 800, 800 }, + .hfront_porch = { 1, 40, 255 }, + .hback_porch = { 88, 88, 88 }, + .hsync_len = { 1, 48, 255 }, + .vactive = { 480, 480, 480 }, + .vfront_porch = { 1, 13, 255 }, + .vback_porch = { 32, 32, 32 }, + .vsync_len = { 3, 3, 255 }, + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | + DISPLAY_FLAGS_SYNC_POSEDGE, +}; + +static const struct panel_desc displaytech_dt050tft_pts = { + .timings = &displaytech_dt050tft_pts_timing, + .num_timings = 1, + .bpc = 8, + .size = { + .width = 121, + .height = 76, + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X24, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | + DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | + DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, + .connector_type = DRM_MODE_CONNECTOR_DPI, +}; + static const struct display_timing dlc_dlc0700yzg_1_timing = { .pixelclock = { 45000000, 51200000, 57000000 }, .hactive = { 1024, 1024, 1024 }, @@ -4015,6 +4045,9 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "dataimage,scf0700c48ggu18", .data = &dataimage_scf0700c48ggu18, + }, { + .compatible = "displaytech,dt050tft-pts", + .data = &displaytech_dt050tft_pts, }, { .compatible = "dlc,dlc0700yzg-1", .data = &dlc_dlc0700yzg_1, -- 2.29.2