From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D96C7C433E6 for ; Wed, 3 Feb 2021 13:41:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8D41864E2E for ; Wed, 3 Feb 2021 13:41:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232093AbhBCNkw (ORCPT ); Wed, 3 Feb 2021 08:40:52 -0500 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:61816 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232157AbhBCNcy (ORCPT ); Wed, 3 Feb 2021 08:32:54 -0500 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 113DPpkD010545; Wed, 3 Feb 2021 05:32:04 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=y1j52uOfzBx3GUao41qAmpabKvsuQHh3Ms1pKkA3Pq8=; b=IH3xgCiQE8hbL9y4gePfkVVuZXw828nxjxaJQ+s1wlsQoepSL3Fpzvc/StlpES6vdIB/ /0r0xEdtIl8u645ox94R5S8r43qxXA0JMGa3O8OfTKZehgVYrkKH0DiAB8oW6Q9l76vh Woxh2PLdTY9XHG1BRr+Q3qWBxzcoVgi73LNsGhfaTMnnO6n2NflQNvvAkgcGhYAbHOxn LlHvV2tdDrAUrPh67uVjjQScAh+MCORJ5VlWjW6KqZuz//RjRwlEZGg3rYG25lTIKkoY v0Kug+OYVHivweIYyjs4xCwO5GULnKRTpd12Cz6SuV+oUl5cWZMRdWtnR4/1e06dCXT6 Hg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 36fnr6154h-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 03 Feb 2021 05:32:04 -0800 Received: from SC-EXCH04.marvell.com (10.93.176.84) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 3 Feb 2021 05:32:03 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 3 Feb 2021 05:32:02 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 3 Feb 2021 05:32:02 -0800 Received: from octopus.marvell.com (octopus.marvell.com [10.5.24.3]) by maili.marvell.com (Postfix) with ESMTP id A32CF3F703F; Wed, 3 Feb 2021 05:31:59 -0800 (PST) From: To: , , CC: , , , , , , , , , , "Konstantin Porotchkin" Subject: [PATCH 05/11] arm64: dts: marvell: armada-3720-db: add comphy references Date: Wed, 3 Feb 2021 15:31:32 +0200 Message-ID: <20210203133138.10754-6-kostap@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210203133138.10754-1-kostap@marvell.com> References: <20210203133138.10754-1-kostap@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369,18.0.737 definitions=2021-02-03_05:2021-02-03,2021-02-03 signatures=0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Grzegorz Jaszczyk Adding phy description to pcie, sata and usb will allow appropriate drivers to configure marvell comphy-a3700 accordingly. Signed-off-by: Grzegorz Jaszczyk Signed-off-by: Konstantin Porotchkin --- arch/arm64/boot/dts/marvell/armada-3720-db.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index 3e5789f37206..15e923f945d4 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -132,11 +132,15 @@ pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; status = "okay"; + /* Generic PHY, providing serdes lanes */ + phys = <&comphy1 0>; }; /* CON3 */ &sata { status = "okay"; + /* Generic PHY, providing serdes lanes */ + phys = <&comphy2 0>; }; &sdhci0 { @@ -217,4 +221,7 @@ &usb3 { status = "okay"; usb-phy = <&usb3_phy>; + /* Generic PHY, providing serdes lanes */ + phys = <&comphy0 0>; + phy-names = "usb"; }; -- 2.17.1