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* [PATCH v3 1/8] dt-bindings: usb: convert rockchip,dwc3.txt to yaml
@ 2021-02-05 11:40 Johan Jonker
  2021-02-05 11:40 ` [PATCH v3 2/8] arm64: dts: rockchip: optimize clks for rk3399 dwc3 Johan Jonker
                   ` (6 more replies)
  0 siblings, 7 replies; 10+ messages in thread
From: Johan Jonker @ 2021-02-05 11:40 UTC (permalink / raw)
  To: heiko
  Cc: robh+dt, gregkh, balbi, linux-usb, devicetree, linux-rockchip,
	linux-arm-kernel, linux-kernel

In the past Rockchip dwc3 usb nodes were manually checked.
With the conversion of snps,dwc3.yaml as common document
we now can convert rockchip,dwc3.txt to yaml as well.
Remove node wrapper.

Added properties for rk3399 are:
  power-domains
  resets
  reset-names

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Changed V3:
  remove aclk_usb3_rksoc_axi_perf
  remove aclk_usb3

Changed V2:
  remove node wrapper
---
 .../devicetree/bindings/usb/rockchip,dwc3.txt      | 56 -------------
 .../devicetree/bindings/usb/rockchip,dwc3.yaml     | 95 ++++++++++++++++++++++
 2 files changed, 95 insertions(+), 56 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
 create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml

diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
deleted file mode 100644
index 945204932..000000000
--- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-Rockchip SuperSpeed DWC3 USB SoC controller
-
-Required properties:
-- compatible:	should contain "rockchip,rk3399-dwc3" for rk3399 SoC
-- clocks:	A list of phandle + clock-specifier pairs for the
-		clocks listed in clock-names
-- clock-names:	Should contain the following:
-  "ref_clk"	Controller reference clk, have to be 24 MHz
-  "suspend_clk"	Controller suspend clk, have to be 24 MHz or 32 KHz
-  "bus_clk"	Master/Core clock, have to be >= 62.5 MHz for SS
-		operation and >= 30MHz for HS operation
-  "grf_clk"	Controller grf clk
-
-Required child node:
-A child node must exist to represent the core DWC3 IP block. The name of
-the node is not important. The content of the node is defined in dwc3.txt.
-
-Phy documentation is provided in the following places:
-Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml - USB2.0 PHY
-Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt     - Type-C PHY
-
-Example device nodes:
-
-	usbdrd3_0: usb@fe800000 {
-		compatible = "rockchip,rk3399-dwc3";
-		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
-			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
-		clock-names = "ref_clk", "suspend_clk",
-			      "bus_clk", "grf_clk";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-		usbdrd_dwc3_0: dwc3@fe800000 {
-			compatible = "snps,dwc3";
-			reg = <0x0 0xfe800000 0x0 0x100000>;
-			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
-			dr_mode = "otg";
-		};
-	};
-
-	usbdrd3_1: usb@fe900000 {
-		compatible = "rockchip,rk3399-dwc3";
-		clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
-			 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
-		clock-names = "ref_clk", "suspend_clk",
-			      "bus_clk", "grf_clk";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-		usbdrd_dwc3_1: dwc3@fe900000 {
-			compatible = "snps,dwc3";
-			reg = <0x0 0xfe900000 0x0 0x100000>;
-			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-			dr_mode = "otg";
-		};
-	};
diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
new file mode 100644
index 000000000..d815aacfc
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SuperSpeed DWC3 USB SoC controller
+
+maintainers:
+  - Heiko Stuebner <heiko@sntech.de>
+
+description:
+  The common content of the node is defined in snps,dwc3.yaml.
+
+  Phy documentation is provided in the following places.
+
+  USB2.0 PHY
+  Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
+
+  Type-C PHY
+  Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
+
+allOf:
+  - $ref: snps,dwc3.yaml#
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - rockchip,rk3399-dwc3
+      - const: snps,dwc3
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description:
+          Controller reference clock, must to be 24 MHz
+      - description:
+          Controller suspend clock, must to be 24 MHz or 32 KHz
+      - description:
+          Master/Core clock, must to be >= 62.5 MHz for SS
+          operation and >= 30MHz for HS operation
+      - description:
+          Controller grf clock
+
+  clock-names:
+    items:
+      - const: ref_clk
+      - const: suspend_clk
+      - const: bus_clk
+      - const: grf_clk
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    const: usb3-otg
+
+unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+
+examples:
+  - |
+    #include <dt-bindings/clock/rk3399-cru.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    bus {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      usbdrd3_0: usb@fe800000 {
+        compatible = "rockchip,rk3399-dwc3", "snps,dwc3";
+        reg = <0x0 0xfe800000 0x0 0x100000>;
+        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
+                 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
+        clock-names = "ref_clk", "suspend_clk",
+                      "bus_clk", "grf_clk";
+        dr_mode = "otg";
+      };
+    };
-- 
2.11.0


^ permalink raw reply related	[flat|nested] 10+ messages in thread
* Re: [PATCH v3 3/8] arm64: dts: rockchip: restyle rk3399 usbdrd3_0 node
@ 2021-02-05 14:19 Mark Kettenis
  0 siblings, 0 replies; 10+ messages in thread
From: Mark Kettenis @ 2021-02-05 14:19 UTC (permalink / raw)
  To: Johan Jonker; +Cc: linux-arm-kernel, devicetree

> For rk3399 dwc3 usb the wrapper node for only clocks makes no sense,
> so restyle the rk3399 usbdrd3_0 node before more new SoC types are
> added with the same IP.
> 
> Signed-off-by: Johan Jonker <jbx6244 at gmail.com>
> ---
> Changed V3:
>   remove aclk_usb3_rksoc_axi_perf
>   remove aclk_usb3
> ---
>  arch/arm64/boot/dts/rockchip/rk3399-ficus.dts      |  2 +-
>  arch/arm64/boot/dts/rockchip/rk3399-firefly.dts    |  6 +---
>  arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi       |  6 +---
>  arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts |  6 +---
>  .../boot/dts/rockchip/rk3399-khadas-edge.dtsi      |  6 +---
>  arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts  |  6 +---
>  arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi   |  4 ---
>  arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts   |  6 +---
>  .../boot/dts/rockchip/rk3399-pinebook-pro.dts      |  4 ---
>  .../arm64/boot/dts/rockchip/rk3399-puma-haikou.dts |  4 ---
>  arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi    |  4 ---
>  arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi |  6 +---
>  arch/arm64/boot/dts/rockchip/rk3399-rock960.dts    |  2 +-
>  arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi   |  4 ---
>  arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi |  6 +---
>  arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi  |  6 +---
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi           | 37 ++++++++--------------
>  .../boot/dts/rockchip/rk3399pro-vmarc-som.dtsi     |  4 ---
>  18 files changed, 24 insertions(+), 95 deletions(-)

This change is problematic since:

-    	    compatible = "rockchip,rk3399-dwc3";
+    	    compatible = "rockchip,rk3399-dwc3", "snps,dwc3";

This means that an existing "glue" driver will now attach to the node
for the actual DWC3 controller.  Not sure what the consequences
exactly are on Linux, but on other systems that consume device trees
(e.g. U-Boot, OpenBSD) this may break things because only the glue
driver attaches.  And even if on Linux both the "glue" driver and the
"core" driver can share a single device tree node, this will still lead to
multiple drivers manipulating the same clocks and resets, which I
think is undesirable.

You could introduce a new rk3399-specific compatible for the node.
But I don't think this device tree binding change is helpful.

Cheers,

Mark

^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-02-05 23:13 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-02-05 11:40 [PATCH v3 1/8] dt-bindings: usb: convert rockchip,dwc3.txt to yaml Johan Jonker
2021-02-05 11:40 ` [PATCH v3 2/8] arm64: dts: rockchip: optimize clks for rk3399 dwc3 Johan Jonker
2021-02-05 11:40 ` [PATCH v3 3/8] arm64: dts: rockchip: restyle rk3399 usbdrd3_0 node Johan Jonker
2021-02-05 11:40 ` [PATCH v3 4/8] arm64: dts: rockchip: restyle rk3399 usbdrd3_1 node Johan Jonker
2021-02-05 11:40 ` [PATCH v3 5/8] dt-bindings: usb: dwc3: add description for rk3328 Johan Jonker
2021-02-05 11:40 ` [PATCH v3 6/8] usb: dwc3: of-simple: add compatible " Johan Jonker
2021-02-05 18:41   ` Rob Herring
2021-02-05 11:40 ` [PATCH v3 7/8] arm64: dts: rockchip: add rk3328 dwc3 usb controller node Johan Jonker
2021-02-05 11:40 ` [PATCH v3 8/8] dts64: rockchip: enable dwc3 usb for A95X Z2 Johan Jonker
  -- strict thread matches above, loose matches on Subject: below --
2021-02-05 14:19 [PATCH v3 3/8] arm64: dts: rockchip: restyle rk3399 usbdrd3_0 node Mark Kettenis

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