Re: [PATCH V8 01/12] dt-bindings: soc: Add dvfsrc driver bindings

[Rob Herring <robh@kernel.org>]

On Tue, Jan 26, 2021 at 04:03:43PM +0800, Henry Chen wrote:
> Document the binding for enabling dvfsrc on MediaTek SoC.
> 
> Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
> ---
>  .../devicetree/bindings/soc/mediatek/dvfsrc.yaml   | 67 ++++++++++++++++++++++
>  include/dt-bindings/interconnect/mtk,mt8183-emi.h  | 21 +++++++
>  2 files changed, 88 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
>  create mode 100644 include/dt-bindings/interconnect/mtk,mt8183-emi.h
> 
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
> new file mode 100644
> index 0000000..0b746a8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/soc/mediatek/dvfsrc.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: MediaTek dynamic voltage and frequency scaling resource collector (DVFSRC)
> +
> +description: |
> +  The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a
> +  HW module which is used to collect all the requests from both software and
> +  hardware and turn into the decision of minimum operating voltage and minimum
> +  DRAM frequency to fulfill those requests.
> +
> +maintainers:
> +  - henryc.chen <henryc.chen@mediatek.com>
> +
> +properties:
> +  reg:
> +    description: DVFSRC common register address and length.

maxItems: 1

> +
> +  compatible:
> +    enum:
> +      - mediatek,mt6873-dvfsrc
> +      - mediatek,mt8183-dvfsrc
> +      - mediatek,mt8192-dvfsrc
> +
> +  '#interconnect-cells':
> +    const: 1
> +
> +patternProperties:
> +  dvfsrc-vcore:

Not a pattern. Move to 'properties'.

> +    type: object
> +    description:
> +      The DVFSRC regulator is modelled as a subdevice of the DVFSRC.
> +      Because DVFSRC can request power directly via register read/write, likes
> +      vcore which is a core power of mt8183. As such, the DVFSRC regulator
> +      requires that DVFSRC nodes be present.
> +    $ref: /schemas/regulator/regulator.yaml#
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#interconnect-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interconnect/mtk,mt8183-emi.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        dvfsrc@10012000 {
> +            compatible = "mediatek,mt8183-dvfsrc";
> +            reg = <0 0x10012000 0 0x1000>;
> +            #interconnect-cells = <1>;
> +            dvfsrc_vcore: dvfsrc-vcore {
> +                    regulator-name = "dvfsrc-vcore";
> +                    regulator-min-microvolt = <725000>;
> +                    regulator-max-microvolt = <800000>;
> +                    regulator-always-on;
> +            };
> +        };
> +    };
> diff --git a/include/dt-bindings/interconnect/mtk,mt8183-emi.h b/include/dt-bindings/interconnect/mtk,mt8183-emi.h
> new file mode 100644
> index 0000000..dfd143f
> --- /dev/null
> +++ b/include/dt-bindings/interconnect/mtk,mt8183-emi.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#ifndef __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H
> +#define __DT_BINDINGS_INTERCONNECT_MTK_MT8183_EMI_H
> +
> +#define MT8183_SLAVE_DDR_EMI			0
> +#define MT8183_MASTER_MCUSYS			1
> +#define MT8183_MASTER_GPU			2
> +#define MT8183_MASTER_MMSYS			3
> +#define MT8183_MASTER_MM_VPU			4
> +#define MT8183_MASTER_MM_DISP			5
> +#define MT8183_MASTER_MM_VDEC			6
> +#define MT8183_MASTER_MM_VENC			7
> +#define MT8183_MASTER_MM_CAM			8
> +#define MT8183_MASTER_MM_IMG			9
> +#define MT8183_MASTER_MM_MDP			10
> +
> +#endif
> -- 
> 1.9.1
>