From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A895DC433E6 for ; Mon, 8 Feb 2021 11:51:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 60AFD64E6E for ; Mon, 8 Feb 2021 11:51:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233479AbhBHLu1 (ORCPT ); Mon, 8 Feb 2021 06:50:27 -0500 Received: from mx07-00178001.pphosted.com ([185.132.182.106]:37649 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233475AbhBHLsW (ORCPT ); Mon, 8 Feb 2021 06:48:22 -0500 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 118Bl2tP019426; Mon, 8 Feb 2021 12:47:19 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=selector1; bh=uLUxLU+qfYHwwCSpsc0nmoBAGh3ZTi70jEcKsAoLbJQ=; b=YxYHAD4SMPuXpD4fZ35bT8RM6N7QEZp35uUEYPqg+6QUi2xw9anZAL8bRLT/2AraBKRW aB5tExjrqI3G11sZioyDiz8J0IUv779w4fm2IGD7/joSmf2umP7IrJWpCPsrwoSiX8YS K6ZXt5TQYXwwTkGy/3blk1v0DpOxr14Ntc71WwhzsVfN7cxR7b6WN7m1H2bE5G215QvW MpUEaMustoq1P/NEYW2KU+CcAcvEx4DPk3AgyeGWxA4ESdD7Eeie8nc0xms2xeBjWzFH unJ2cpT80Vghms49I29Az52cMVw3YgNmQovcWWQdK/K3GnE/tDXXQBcrsAcxDaaTaV8H Rw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 36hr319qve-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 08 Feb 2021 12:47:19 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id AE2C510002A; Mon, 8 Feb 2021 12:47:18 +0100 (CET) Received: from Webmail-eu.st.com (gpxdag2node6.st.com [10.75.127.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A159223C7C6; Mon, 8 Feb 2021 12:47:18 +0100 (CET) Received: from localhost (10.75.127.117) by GPXDAG2NODE6.st.com (10.75.127.70) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 8 Feb 2021 12:47:17 +0100 From: Amelie Delaunay To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Alexandre Torgue , Maxime Coquelin CC: , , , , Amelie Delaunay Subject: [PATCH v3 2/2] phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock Date: Mon, 8 Feb 2021 12:46:59 +0100 Message-ID: <20210208114659.15269-3-amelie.delaunay@foss.st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210208114659.15269-1-amelie.delaunay@foss.st.com> References: <20210208114659.15269-1-amelie.delaunay@foss.st.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.75.127.117] X-ClientProxiedBy: GPXDAG1NODE6.st.com (10.75.127.67) To GPXDAG2NODE6.st.com (10.75.127.70) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369,18.0.737 definitions=2021-02-08_03:2021-02-08,2021-02-08 signatures=0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org ck_usbo_48m is generated by usbphyc PLL and used by OTG controller for Full-Speed use cases with dedicated Full-Speed transceiver. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by: Amelie Delaunay --- Changes in v2: - fix COMMON_CLK dependency issue reported by kernel test robot --- drivers/phy/st/Kconfig | 1 + drivers/phy/st/phy-stm32-usbphyc.c | 65 ++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/drivers/phy/st/Kconfig b/drivers/phy/st/Kconfig index b32f44ff9033..3fc3d0781fb8 100644 --- a/drivers/phy/st/Kconfig +++ b/drivers/phy/st/Kconfig @@ -36,6 +36,7 @@ config PHY_STIH407_USB config PHY_STM32_USBPHYC tristate "STMicroelectronics STM32 USB HS PHY Controller driver" depends on ARCH_STM32 || COMPILE_TEST + depends on COMMON_CLK select GENERIC_PHY help Enable this to support the High-Speed USB transceivers that are part diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c index d08fbb180e43..c184f4e34584 100644 --- a/drivers/phy/st/phy-stm32-usbphyc.c +++ b/drivers/phy/st/phy-stm32-usbphyc.c @@ -7,6 +7,7 @@ */ #include #include +#include #include #include #include @@ -70,6 +71,7 @@ struct stm32_usbphyc { struct regulator *vdda1v1; struct regulator *vdda1v8; atomic_t n_pll_cons; + struct clk_hw clk48_hw; int switch_setup; }; @@ -295,6 +297,61 @@ static const struct phy_ops stm32_usbphyc_phy_ops = { .owner = THIS_MODULE, }; +static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw) +{ + struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw); + + return stm32_usbphyc_pll_enable(usbphyc); +} + +static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw) +{ + struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw); + + stm32_usbphyc_pll_disable(usbphyc); +} + +static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + return 48000000; +} + +static const struct clk_ops usbphyc_clk48_ops = { + .prepare = stm32_usbphyc_clk48_prepare, + .unprepare = stm32_usbphyc_clk48_unprepare, + .recalc_rate = stm32_usbphyc_clk48_recalc_rate, +}; + +static void stm32_usbphyc_clk48_unregister(void *data) +{ + struct stm32_usbphyc *usbphyc = data; + + of_clk_del_provider(usbphyc->dev->of_node); + clk_hw_unregister(&usbphyc->clk48_hw); +} + +static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc) +{ + struct device_node *node = usbphyc->dev->of_node; + struct clk_init_data init = { }; + int ret = 0; + + init.name = "ck_usbo_48m"; + init.ops = &usbphyc_clk48_ops; + + usbphyc->clk48_hw.init = &init; + + ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw); + if (ret) + return ret; + + ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw); + if (ret) + clk_hw_unregister(&usbphyc->clk48_hw); + + return ret; +} + static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc, u32 utmi_switch) { @@ -473,6 +530,12 @@ static int stm32_usbphyc_probe(struct platform_device *pdev) goto clk_disable; } + ret = stm32_usbphyc_clk48_register(usbphyc); + if (ret) { + dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret); + goto clk_disable; + } + version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION); dev_info(dev, "registered rev:%lu.%lu\n", FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version)); @@ -497,6 +560,8 @@ static int stm32_usbphyc_remove(struct platform_device *pdev) if (usbphyc->phys[port]->active) stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy); + stm32_usbphyc_clk48_unregister(usbphyc); + clk_disable_unprepare(usbphyc->clk); return 0; -- 2.17.1