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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id p67sm777226oih.21.2021.02.10.14.55.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 14:55:08 -0800 (PST) Received: (nullmailer pid 2967891 invoked by uid 1000); Wed, 10 Feb 2021 22:54:12 -0000 Date: Wed, 10 Feb 2021 16:54:12 -0600 From: Rob Herring To: Irui Wang Cc: Alexandre Courbot , Hans Verkuil , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Matthias Brugger , Fritz Koenig , Tzung-Bi Shih , Maoguang Meng , Longfei Wang , Yunfei Dong , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, srv_heupstream@mediatek.com, linux-mediatek@lists.infradead.org Subject: Re: [PATCH 3/5] dt-bindings: media: mtk-vcodec: Add binding for MT8192 VENC Message-ID: <20210210225412.GA2966579@robh.at.kernel.org> References: <20210203083752.12586-1-irui.wang@mediatek.com> <20210203083752.12586-4-irui.wang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210203083752.12586-4-irui.wang@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Feb 03, 2021 at 04:37:50PM +0800, Irui Wang wrote: > Updates binding document for mt8192 encoder driver. > > Signed-off-by: Irui Wang > --- > .../bindings/media/mediatek-vcodec.txt | 26 +++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > index e4644f8caee9..c7fac557006f 100644 > --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > @@ -9,6 +9,7 @@ Required properties: > "mediatek,mt8173-vcodec-avc-enc" for mt8173 avc encoder. > "mediatek,mt8183-vcodec-enc" for MT8183 encoder. > "mediatek,mt8173-vcodec-dec" for MT8173 decoder. > + "mediatek,mt8192-vcodec-enc" for MT8192 encoder. > - reg : Physical base address of the video codec registers and length of > memory mapped region. > - interrupts : interrupt number to the cpu. > @@ -128,3 +129,28 @@ vcodec_enc_lt: vcodec@19002000 { > assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; > assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>; > }; > + > +vcodec_enc: vcodec@0x17020000 { Don't add an example just for a new compatible. > + compatible = "mediatek,mt8192-vcodec-enc"; > + reg = <0 0x17020000 0 0x2000>; > + iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, > + <&iommu0 M4U_PORT_L7_VENC_REC>, > + <&iommu0 M4U_PORT_L7_VENC_BSDMA>, > + <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, > + <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, > + <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, > + <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, > + <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, > + <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, > + <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, > + <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; > + interrupts = ; > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; > + mediatek,scp = <&scp>; > + power-domains = <&scpsys MT8192_POWER_DOMAIN_VENC>; > + clocks = <&vencsys CLK_VENC_SET1_VENC>; > + clock-names = "venc-set1"; > + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; > + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; > +}; > + > -- > 2.25.1 >