From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
To: ezequiel@collabora.com, p.zabel@pengutronix.de,
mchehab@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de,
festevam@gmail.com, linux-imx@nxp.com,
gregkh@linuxfoundation.org, mripard@kernel.org,
paul.kocialkowski@bootlin.com, wens@csie.org,
jernej.skrabec@siol.net, krzk@kernel.org, shengjiu.wang@nxp.com,
adrian.ratiu@collabora.com, aisheng.dong@nxp.com,
peng.fan@nxp.com, Anson.Huang@nxp.com, hverkuil-cisco@xs4all.nl
Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devel@driverdev.osuosl.org,
kernel@collabora.com,
Benjamin Gaignard <benjamin.gaignard@collabora.com>
Subject: [PATCH v1 04/18] media: hevc: add structures for hevc codec
Date: Wed, 17 Feb 2021 09:02:52 +0100 [thread overview]
Message-ID: <20210217080306.157876-5-benjamin.gaignard@collabora.com> (raw)
In-Reply-To: <20210217080306.157876-1-benjamin.gaignard@collabora.com>
Define additional structures to be used by HEVC codecs.
This will allow to provide the needed information to the
hardware block.
Adapt Cedrus driver to use these new structures
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Signed-off-by: Adrian Ratiu <adrian.ratiu@collabora.com>
---
drivers/staging/media/sunxi/cedrus/cedrus.c | 6 +++
drivers/staging/media/sunxi/cedrus/cedrus.h | 1 +
.../staging/media/sunxi/cedrus/cedrus_dec.c | 2 +
.../staging/media/sunxi/cedrus/cedrus_h265.c | 6 ++-
include/media/hevc-ctrls.h | 52 ++++++++++++++++---
5 files changed, 57 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
index 7bd9291c8d5f..4cd3cab1a257 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
@@ -151,6 +151,12 @@ static const struct cedrus_control cedrus_controls[] = {
},
.codec = CEDRUS_CODEC_VP8,
},
+ {
+ .cfg = {
+ .id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS,
+ },
+ .codec = CEDRUS_CODEC_H265,
+ },
};
#define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls)
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h
index 251a6a660351..c18b7f7a2820 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus.h
+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
@@ -76,6 +76,7 @@ struct cedrus_h265_run {
const struct v4l2_ctrl_hevc_sps *sps;
const struct v4l2_ctrl_hevc_pps *pps;
const struct v4l2_ctrl_hevc_slice_params *slice_params;
+ const struct v4l2_ctrl_hevc_decode_params *decode_params;
};
struct cedrus_vp8_run {
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c
index a9090daf626a..cd821f417a14 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c
@@ -68,6 +68,8 @@ void cedrus_device_run(void *priv)
V4L2_CID_MPEG_VIDEO_HEVC_PPS);
run.h265.slice_params = cedrus_find_control_data(ctx,
V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS);
+ run.h265.decode_params = cedrus_find_control_data(ctx,
+ V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS);
break;
case V4L2_PIX_FMT_VP8_FRAME:
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
index ce497d0197df..dce5db6be13a 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
@@ -245,6 +245,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
const struct v4l2_ctrl_hevc_sps *sps;
const struct v4l2_ctrl_hevc_pps *pps;
const struct v4l2_ctrl_hevc_slice_params *slice_params;
+ const struct v4l2_ctrl_hevc_decode_params *decode_params;
const struct v4l2_hevc_pred_weight_table *pred_weight_table;
dma_addr_t src_buf_addr;
dma_addr_t src_buf_end_addr;
@@ -256,6 +257,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
sps = run->h265.sps;
pps = run->h265.pps;
slice_params = run->h265.slice_params;
+ decode_params = run->h265.decode_params;
pred_weight_table = &slice_params->pred_weight_table;
/* MV column buffer size and allocation. */
@@ -487,7 +489,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
reg = VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(slice_params->slice_tc_offset_div2) |
VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(slice_params->slice_beta_offset_div2) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(slice_params->num_rps_poc_st_curr_after == 0) |
+ VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(decode_params->num_rps_poc_st_curr_after == 0) |
VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(slice_params->slice_cr_qp_offset) |
VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(slice_params->slice_cb_qp_offset) |
VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(slice_params->slice_qp_delta);
@@ -528,7 +530,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
/* Write decoded picture buffer in pic list. */
cedrus_h265_frame_info_write_dpb(ctx, slice_params->dpb,
- slice_params->num_active_dpb_entries);
+ decode_params->num_active_dpb_entries);
/* Output frame. */
diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h
index ce503bbcb441..799c81612242 100644
--- a/include/media/hevc-ctrls.h
+++ b/include/media/hevc-ctrls.h
@@ -58,6 +58,9 @@ enum v4l2_mpeg_video_hevc_start_code {
/* The controls are not stable at the moment and will likely be reworked. */
struct v4l2_ctrl_hevc_sps {
/* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */
+ __u8 video_parameter_set_id;
+ __u8 seq_parameter_set_id;
+ __u8 chroma_format_idc;
__u16 pic_width_in_luma_samples;
__u16 pic_height_in_luma_samples;
__u8 bit_depth_luma_minus8;
@@ -78,9 +81,9 @@ struct v4l2_ctrl_hevc_sps {
__u8 log2_diff_max_min_pcm_luma_coding_block_size;
__u8 num_short_term_ref_pic_sets;
__u8 num_long_term_ref_pics_sps;
- __u8 chroma_format_idc;
- __u8 padding;
+ __u8 num_slices;
+ __u8 padding[6];
__u64 flags;
};
@@ -104,10 +107,15 @@ struct v4l2_ctrl_hevc_sps {
#define V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER (1ULL << 16)
#define V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT (1ULL << 17)
#define V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT (1ULL << 18)
+#define V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT (1ULL << 19)
+#define V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING (1ULL << 20)
struct v4l2_ctrl_hevc_pps {
/* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */
+ __u8 pic_parameter_set_id;
__u8 num_extra_slice_header_bits;
+ __u8 num_ref_idx_l0_default_active_minus1;
+ __u8 num_ref_idx_l1_default_active_minus1;
__s8 init_qp_minus26;
__u8 diff_cu_qp_delta_depth;
__s8 pps_cb_qp_offset;
@@ -120,7 +128,7 @@ struct v4l2_ctrl_hevc_pps {
__s8 pps_tc_offset_div2;
__u8 log2_parallel_merge_level_minus2;
- __u8 padding[4];
+ __u8 padding;
__u64 flags;
};
@@ -169,6 +177,10 @@ struct v4l2_ctrl_hevc_slice_params {
__u32 bit_size;
__u32 data_bit_offset;
+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
+ __u32 slice_segment_addr;
+ __u32 num_entry_point_offsets;
+
/* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */
__u8 nal_unit_type;
__u8 nuh_temporal_id_plus1;
@@ -194,15 +206,13 @@ struct v4l2_ctrl_hevc_slice_params {
__u8 pic_struct;
/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
- __u8 num_active_dpb_entries;
__u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
__u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
- __u8 num_rps_poc_st_curr_before;
- __u8 num_rps_poc_st_curr_after;
- __u8 num_rps_poc_lt_curr;
+ __u16 short_term_ref_pic_set_size;
+ __u16 long_term_ref_pic_set_size;
- __u8 padding;
+ __u8 padding[5];
/* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
@@ -213,4 +223,30 @@ struct v4l2_ctrl_hevc_slice_params {
__u64 flags;
};
+#define V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC 0x1
+#define V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC 0x2
+#define V4L2_HEVC_DECODE_PARAM_FLAG_NO_OUTPUT_OF_PRIOR 0x4
+
+struct v4l2_ctrl_hevc_decode_params {
+ __s32 pic_order_cnt_val;
+ __u8 num_active_dpb_entries;
+ struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
+ __u8 num_rps_poc_st_curr_before;
+ __u8 num_rps_poc_st_curr_after;
+ __u8 num_rps_poc_lt_curr;
+ __u8 rps_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
+ __u8 rps_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
+ __u8 rps_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
+ __u64 flags;
+};
+
+struct v4l2_ctrl_hevc_scaling_matrix {
+ __u8 scaling_list_4x4[6][16];
+ __u8 scaling_list_8x8[6][64];
+ __u8 scaling_list_16x16[6][64];
+ __u8 scaling_list_32x32[2][64];
+ __u8 scaling_list_dc_coef_16x16[6];
+ __u8 scaling_list_dc_coef_32x32[2];
+};
+
#endif
--
2.25.1
next prev parent reply other threads:[~2021-02-17 8:04 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-17 8:02 [PATCH v1 00/18] Add HANTRO G2/HEVC decoder support for IMX8MQ Benjamin Gaignard
2021-02-17 8:02 ` [PATCH v1 01/18] include: media: hevc: Add scaling and decode params controls Benjamin Gaignard
2021-02-17 8:02 ` [PATCH v1 02/18] media: hantro: Define HEVC codec profiles and supported features Benjamin Gaignard
2021-02-17 19:31 ` Ezequiel Garcia
2021-02-17 8:02 ` [PATCH v1 03/18] arm64: dts: imx8mq-evk: add reserve memory node for CMA region Benjamin Gaignard
2021-02-17 19:39 ` Ezequiel Garcia
2021-02-18 10:15 ` Lucas Stach
2021-02-18 10:45 ` Dan Carpenter
2021-02-17 8:02 ` Benjamin Gaignard [this message]
2021-02-17 19:54 ` [PATCH v1 04/18] media: hevc: add structures for hevc codec Ezequiel Garcia
2021-02-17 8:02 ` [PATCH v1 05/18] media: controls: Add control for HEVC codec Benjamin Gaignard
2021-02-17 19:58 ` Ezequiel Garcia
2021-02-17 8:02 ` [PATCH v1 06/18] media: hantro: Make sure that ctx->codex_ops is set Benjamin Gaignard
2021-02-17 20:11 ` Ezequiel Garcia
2021-02-18 10:53 ` Dan Carpenter
2021-02-17 8:02 ` [PATCH v1 07/18] media: hantro: Add a field to distinguish the hardware versions Benjamin Gaignard
2021-02-17 20:15 ` Ezequiel Garcia
2021-02-18 10:55 ` Dan Carpenter
2021-02-17 8:02 ` [PATCH v1 08/18] media: hantro: Add HEVC structures Benjamin Gaignard
2021-02-17 8:02 ` [PATCH v1 09/18] media: hantro: move hantro_needs_postproc function Benjamin Gaignard
2021-02-18 10:59 ` Dan Carpenter
2021-02-17 8:02 ` [PATCH v1 10/18] media: hantro: Add helper functions for buffer information Benjamin Gaignard
2021-02-17 20:31 ` Ezequiel Garcia
2021-02-17 8:02 ` [PATCH v1 11/18] media: hantro: Add helper function for auxiliary buffers allocation Benjamin Gaignard
2021-02-17 20:42 ` Ezequiel Garcia
2021-02-18 14:51 ` Benjamin Gaignard
2021-02-17 8:03 ` [PATCH v1 12/18] media: uapi: Add a control for HANTRO driver Benjamin Gaignard
2021-02-17 8:03 ` [PATCH v1 13/18] media: hantro: Introduce G2/HEVC decoder Benjamin Gaignard
2021-02-17 20:45 ` Ezequiel Garcia
2021-02-18 10:43 ` Benjamin Gaignard
2021-02-18 11:47 ` Dan Carpenter
2021-02-17 8:03 ` [PATCH v1 14/18] media: hantro: add G2 support to postproc Benjamin Gaignard
2021-02-17 8:03 ` [PATCH v1 15/18] media: hantro: handle V4L2_PIX_FMT_HEVC_SLICE control Benjamin Gaignard
2021-02-17 20:13 ` Ezequiel Garcia
2021-02-17 8:03 ` [PATCH v1 16/18] media: hantro: IMX8M: add variant for G2/HEVC codec Benjamin Gaignard
2021-02-17 8:03 ` [PATCH v1 17/18] dt-bindings: media: nxp,imx8mq-vpu: Update bindings Benjamin Gaignard
2021-02-17 22:48 ` Rob Herring
2021-02-18 14:48 ` Benjamin Gaignard
2021-02-17 8:03 ` [PATCH v1 18/18] arm64: dts: imx8mq: Add node to G2 hardware Benjamin Gaignard
2021-02-17 20:43 ` Ezequiel Garcia
2021-02-18 15:47 ` Benjamin Gaignard
2021-02-17 8:08 ` [PATCH v1 00/18] Add HANTRO G2/HEVC decoder support for IMX8MQ Greg KH
2021-02-17 8:28 ` Benjamin Gaignard
2021-02-17 8:36 ` Greg KH
2021-02-17 9:10 ` Hans Verkuil
2021-02-17 9:23 ` Greg KH
2021-02-17 8:38 ` Paul Kocialkowski
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