From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D452C433E0 for ; Thu, 18 Feb 2021 08:54:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 38A9164E92 for ; Thu, 18 Feb 2021 08:54:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229769AbhBRIxr convert rfc822-to-8bit (ORCPT ); Thu, 18 Feb 2021 03:53:47 -0500 Received: from mslow2.mail.gandi.net ([217.70.178.242]:60717 "EHLO mslow2.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231132AbhBRIu4 (ORCPT ); Thu, 18 Feb 2021 03:50:56 -0500 Received: from relay11.mail.gandi.net (unknown [217.70.178.231]) by mslow2.mail.gandi.net (Postfix) with ESMTP id C82C13AF92B for ; Thu, 18 Feb 2021 08:40:34 +0000 (UTC) Received: from xps13 (lfbn-tou-1-972-113.w86-210.abo.wanadoo.fr [86.210.203.113]) (Authenticated sender: miquel.raynal@bootlin.com) by relay11.mail.gandi.net (Postfix) with ESMTPSA id 39B6B100015; Thu, 18 Feb 2021 08:37:16 +0000 (UTC) Date: Thu, 18 Feb 2021 09:37:15 +0100 From: Miquel Raynal To: Shubhrajyoti Datta Cc: , , , , , Subject: Re: [PATCH v9 6/7] clk: clock-wizard: Remove the hardcoding of the clock outputs Message-ID: <20210218093715.7fdc27ee@xps13> In-Reply-To: <1613623791-4598-7-git-send-email-shubhrajyoti.datta@xilinx.com> References: <1613623791-4598-1-git-send-email-shubhrajyoti.datta@xilinx.com> <1613623791-4598-7-git-send-email-shubhrajyoti.datta@xilinx.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.4 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Shubhrajyoti, Shubhrajyoti Datta wrote on Thu, 18 Feb 2021 10:19:50 +0530: > The number of output clocks are configurable in the hardware. > Currently the driver registers the maximum number of outputs. > Fix the same by registering only the outputs that are there. > > Signed-off-by: Shubhrajyoti Datta > --- > v4: > Assign output in this patch > > drivers/clk/clk-xlnx-clock-wizard.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c > index ed3b0ef..d403a74 100644 > --- a/drivers/clk/clk-xlnx-clock-wizard.c > +++ b/drivers/clk/clk-xlnx-clock-wizard.c > @@ -473,6 +473,7 @@ static int clk_wzrd_probe(struct platform_device *pdev) > unsigned long rate; > const char *clk_name; > struct clk_wzrd *clk_wzrd; > + int outputs; > struct device_node *np = pdev->dev.of_node; > > clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL); > @@ -541,6 +542,7 @@ static int clk_wzrd_probe(struct platform_device *pdev) > goto err_disable_clk; > } > > + outputs = of_property_count_strings(np, "clock-output-names"); A check on outputs validity is probably welcome. Also I usually prefer noutputs or nb_outputs for such variable name, which implies a number rather than an array, but this is personal taste. > /* register div */ > reg = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0)) & > WZRD_DIVCLK_DIVIDE_MASK) >> WZRD_DIVCLK_DIVIDE_SHIFT; > @@ -562,7 +564,7 @@ static int clk_wzrd_probe(struct platform_device *pdev) > } > > /* register div per output */ > - for (i = WZRD_NUM_OUTPUTS - 1; i >= 0 ; i--) { > + for (i = outputs - 1; i >= 0 ; i--) { > const char *clkout_name; > > if (of_property_read_string_index(np, "clock-output-names", i, > @@ -593,7 +595,7 @@ static int clk_wzrd_probe(struct platform_device *pdev) > if (IS_ERR(clk_wzrd->clkout[i])) { > int j; > > - for (j = i + 1; j < WZRD_NUM_OUTPUTS; j++) > + for (j = i + 1; j < outputs; j++) > clk_unregister(clk_wzrd->clkout[j]); > dev_err(&pdev->dev, > "unable to register divider clock\n"); Thanks, Miquèl