From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60583C433DB for ; Sat, 27 Feb 2021 13:21:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3447264E67 for ; Sat, 27 Feb 2021 13:21:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230053AbhB0NVU (ORCPT ); Sat, 27 Feb 2021 08:21:20 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:41276 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229953AbhB0NVT (ORCPT ); Sat, 27 Feb 2021 08:21:19 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 11RDKTl2033600; Sat, 27 Feb 2021 07:20:29 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1614432029; bh=wBp27AmyBVyZhxBRGGDoMrwJNFH6LZH2cMDEnKwh5sE=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=Bt/cADFlZO5bnd3xWva8n/gq4Uuo7UBeGS8cZlefZqSJBuXvc3tWM2c/hm3kQ7A/0 TPGGxC9AoQMQpo3lo1+XpOLgtOFy33fq4eKt9iM9ViIRdZauiuxKKJ8td6/GBZA6Bx +lZ6EofeyKUEkfchap2CG2WC2JXSKIliQOgOTDcM= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 11RDKTsV126882 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 27 Feb 2021 07:20:29 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Sat, 27 Feb 2021 07:20:29 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Sat, 27 Feb 2021 07:20:29 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 11RDKTi8117506; Sat, 27 Feb 2021 07:20:29 -0600 Date: Sat, 27 Feb 2021 07:20:29 -0600 From: Nishanth Menon To: Dave Gerlach CC: , , Rob Herring , Tony Lindgren , Vignesh Raghavendra , Suman Anna , Sekhar Nori , Kishon Vijay Abraham , Lokesh Vutla , Aswath Govindraju Subject: Re: [PATCH v4 2/5] dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM64 Message-ID: <20210227132029.tiocrois267kmm66@sandbox> References: <20210226144257.5470-1-d-gerlach@ti.com> <20210226144257.5470-3-d-gerlach@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20210226144257.5470-3-d-gerlach@ti.com> User-Agent: NeoMutt/20171215 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 08:42-20210226, Dave Gerlach wrote: > Add pinctrl macros for AM64 SoC. These macro definitions are similar to > that of previous platforms, but adding new definitions to avoid any > naming confusions in the soc dts files. > > Unlike what checkpatch insists, we do not need parentheses enclosing > the values for this macro as we do intend it to generate two separate > values as has been done for other similar platforms. > > Signed-off-by: Dave Gerlach > Reviewed-by: Grygorii Strashko > Reviewed-by: Suman Anna > Acked-by: Rob Herring > --- > include/dt-bindings/pinctrl/k3.h | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h > index b0eea7cc6e23..e085f102b283 100644 > --- a/include/dt-bindings/pinctrl/k3.h > +++ b/include/dt-bindings/pinctrl/k3.h > @@ -3,7 +3,7 @@ > * This header provides constants for pinctrl bindings for TI's K3 SoC > * family. > * > - * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ > + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ > */ > #ifndef _DT_BINDINGS_PINCTRL_TI_K3_H > #define _DT_BINDINGS_PINCTRL_TI_K3_H > @@ -35,4 +35,7 @@ > #define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) > #define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) > > +#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) > +#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) > + > #endif > -- > 2.28.0 > Just documenting for lore: https://lore.kernel.org/linux-arm-kernel/20210209023418.GA2564097@robh.at.kernel.org/#t is where the ack was picked up from. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D)/Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D