From: Dmitry Osipenko <digetx@gmail.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Mark Brown" <broonie@kernel.org>,
"Paul Fertser" <fercerpav@gmail.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Matt Merhar" <mattmerhar@protonmail.com>,
"Peter Geis" <pgwipeout@gmail.com>,
"Nicolas Chauvet" <kwizart@gmail.com>,
"Viresh Kumar" <vireshk@kernel.org>,
"Stephen Boyd" <sboyd@kernel.org>,
"Michał Mirosław" <mirq-linux@rere.qmqm.pl>,
"Krzysztof Kozlowski" <krzk@kernel.org>
Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v3 3/6] dt-bindings: power: tegra: Add binding for core power domain
Date: Fri, 12 Mar 2021 02:12:05 +0300 [thread overview]
Message-ID: <20210311231208.18180-4-digetx@gmail.com> (raw)
In-Reply-To: <20210311231208.18180-1-digetx@gmail.com>
All NVIDIA Tegra SoCs have a core power domain where majority of hardware
blocks reside. Add binding for the core power domain.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
.../power/nvidia,tegra20-core-domain.yaml | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml
diff --git a/Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml b/Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml
new file mode 100644
index 000000000000..bc68c5757d45
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/nvidia,tegra20-core-domain.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/nvidia,tegra20-core-domain.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Core Power Domain
+
+maintainers:
+ - Dmitry Osipenko <digetx@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+allOf:
+ - $ref: power-domain.yaml#
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra20-core-domain
+ - nvidia,tegra30-core-domain
+
+ operating-points-v2:
+ description:
+ Should contain level, voltages and opp-supported-hw property.
+ The supported-hw is a bitfield indicating SoC speedo or process
+ ID mask.
+
+ "#power-domain-cells":
+ const: 0
+
+ power-supply:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to voltage regulator connected to the SoC Core power rail.
+
+required:
+ - compatible
+ - operating-points-v2
+ - "#power-domain-cells"
+ - power-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ power-domain {
+ compatible = "nvidia,tegra20-core-domain";
+ operating-points-v2 = <&opp_table>;
+ power-supply = <®ulator>;
+ #power-domain-cells = <0>;
+ };
--
2.29.2
next prev parent reply other threads:[~2021-03-11 23:16 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-11 23:12 [PATCH v3 0/6] NVIDIA Tegra core power domain driver and OPP helper Dmitry Osipenko
2021-03-11 23:12 ` [PATCH v3 1/6] soc/tegra: Add devm_tegra_core_dev_init_opp_table() Dmitry Osipenko
2021-03-11 23:12 ` [PATCH v3 2/6] soc/tegra: Add CONFIG_SOC_TEGRA_COMMON and select PM_OPP by default Dmitry Osipenko
2021-03-11 23:12 ` Dmitry Osipenko [this message]
2021-03-12 14:23 ` [PATCH v3 3/6] dt-bindings: power: tegra: Add binding for core power domain Rob Herring
2021-03-11 23:12 ` [PATCH v3 4/6] soc/tegra: Introduce core power domain driver Dmitry Osipenko
2021-03-11 23:12 ` [PATCH v3 5/6] soc/tegra: regulators: Support Core domain state syncing Dmitry Osipenko
2021-03-11 23:12 ` [PATCH v3 6/6] soc/tegra: pmc: Link children power domains to the parent domain Dmitry Osipenko
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