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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Cc: "Stephen Boyd" <sboyd@kernel.org>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Andreas Färber" <afaerber@suse.de>,
	"Michael Turquette" <mturquette@baylibre.com>,
	"Edgar Bernardi Righi" <edgar.righi@lsitec.org.br>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-actions@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH 2/6] clk: actions: Fix SD clocks factor table on Owl S500 SoC
Date: Tue, 16 Mar 2021 09:28:45 +0530	[thread overview]
Message-ID: <20210316035845.GB1798@thinkpad> (raw)
In-Reply-To: <973b08fe414321ba4ade096a4917cadc2013426e.1615221459.git.cristian.ciocaltea@gmail.com>

On Mon, Mar 08, 2021 at 07:18:27PM +0200, Cristian Ciocaltea wrote:
> Drop the unsupported entries in the factor table used for the SD[0-2]
> clocks definitions on the Actions Semi Owl S500 SoC.
> 
> Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> ---
>  drivers/clk/actions/owl-s500.c | 4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
> index 75b7186185b0..69cd959205f5 100644
> --- a/drivers/clk/actions/owl-s500.c
> +++ b/drivers/clk/actions/owl-s500.c
> @@ -127,8 +127,6 @@ static struct clk_factor_table sd_factor_table[] = {
>  	{ 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
>  	{ 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
>  	{ 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
> -	{ 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 },
> -	{ 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 },

How did you determine that these values are not supported?

I've seen cases where the datasheet has the incomplete information about the
supported ranges but the downstream driver has everything.

Thanks,
Mani

>  
>  	/* bit8: /128 */
>  	{ 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
> @@ -137,8 +135,6 @@ static struct clk_factor_table sd_factor_table[] = {
>  	{ 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
>  	{ 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
>  	{ 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
> -	{ 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 },
> -	{ 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 },
>  	{ 0, 0, 0 },
>  };
>  
> -- 
> 2.30.1
> 

  reply	other threads:[~2021-03-16  3:59 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-08 17:18 [PATCH 0/6] Improve clock support for Actions S500 SoC Cristian Ciocaltea
2021-03-08 17:18 ` [PATCH 1/6] clk: actions: Fix UART clock dividers on Owl " Cristian Ciocaltea
2021-03-16  3:50   ` Manivannan Sadhasivam
2021-03-08 17:18 ` [PATCH 2/6] clk: actions: Fix SD clocks factor table " Cristian Ciocaltea
2021-03-16  3:58   ` Manivannan Sadhasivam [this message]
2021-03-16 18:14     ` Cristian Ciocaltea
2021-05-26 10:07       ` Manivannan Sadhasivam
2021-05-27 13:27         ` Cristian Ciocaltea
2021-03-08 17:18 ` [PATCH 3/6] clk: actions: Fix bisp_factor_table based clocks " Cristian Ciocaltea
2021-03-16  4:17   ` Manivannan Sadhasivam
2021-03-16 18:37     ` Cristian Ciocaltea
2021-05-26 10:18       ` Manivannan Sadhasivam
2021-05-27 13:34         ` Cristian Ciocaltea
2021-03-08 17:18 ` [PATCH 4/6] clk: actions: Fix AHPPREDIV-H-AHB clock chain " Cristian Ciocaltea
2021-03-16  5:45   ` Manivannan Sadhasivam
2021-03-16 18:50     ` Cristian Ciocaltea
2021-05-26 10:12       ` Manivannan Sadhasivam
2021-05-27 13:45         ` Cristian Ciocaltea
2021-03-08 17:18 ` [PATCH 5/6] dt-bindings: clock: Add NIC and ETHERNET bindings for Actions " Cristian Ciocaltea
2021-03-16 22:00   ` Rob Herring
2021-03-08 17:18 ` [PATCH 6/6] clk: actions: Add NIC and ETHERNET clock support " Cristian Ciocaltea
2021-03-16  5:52   ` Manivannan Sadhasivam
2021-03-16 19:02     ` Cristian Ciocaltea

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