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[98.128.249.223]) by smtp.gmail.com with ESMTPSA id x23sm3271121lfg.309.2021.03.17.00.18.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 00:18:01 -0700 (PDT) Date: Wed, 17 Mar 2021 08:17:59 +0100 From: Jens Wiklander To: Sudeep Holla Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Trilok Soni , arve@android.com, Andrew Walbran , David Hartley , Achin Gupta , Arunachalam Ganapathy , Marc Bonnici Subject: Re: [PATCH v4 2/7] arm64: smccc: Add support for SMCCCv1.2 input/output registers Message-ID: <20210317071759.GA3005811@jade> References: <20210212154614.38604-1-sudeep.holla@arm.com> <20210212154614.38604-3-sudeep.holla@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210212154614.38604-3-sudeep.holla@arm.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Feb 12, 2021 at 03:46:09PM +0000, Sudeep Holla wrote: > SMCCC v1.2 allows x8-x17 to be used as parameter registers and x4—x17 > to be used as result registers in SMC64/HVC64. Arm Firmware Framework > for Armv8-A specification makes use of x0-x7 as parameter and result > registers. > > Current SMCCC interface in the kernel just use x0-x7 as parameter and > x0-x3 as result registers. Let us add new interface to support x0-x7 > as parameter and result registers. This can be extended to include > x8-x17 when there are users for the same. > > Signed-off-by: Sudeep Holla > --- > arch/arm64/kernel/asm-offsets.c | 4 +++ > arch/arm64/kernel/smccc-call.S | 22 +++++++++++++++ > include/linux/arm-smccc.h | 50 +++++++++++++++++++++++++++++++++ > 3 files changed, 76 insertions(+) > > diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c > index 301784463587..89b444591575 100644 > --- a/arch/arm64/kernel/asm-offsets.c > +++ b/arch/arm64/kernel/asm-offsets.c > @@ -129,6 +129,10 @@ int main(void) > DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2)); > DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id)); > DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state)); > + DEFINE(ARM_SMCCC_V1_2_RES_X0_OFFS, offsetof(struct arm_smccc_v1_2_res, a0)); > + DEFINE(ARM_SMCCC_V1_2_RES_X2_OFFS, offsetof(struct arm_smccc_v1_2_res, a2)); > + DEFINE(ARM_SMCCC_V1_2_RES_X4_OFFS, offsetof(struct arm_smccc_v1_2_res, a4)); > + DEFINE(ARM_SMCCC_V1_2_RES_X6_OFFS, offsetof(struct arm_smccc_v1_2_res, a6)); > BLANK(); > DEFINE(HIBERN_PBE_ORIG, offsetof(struct pbe, orig_address)); > DEFINE(HIBERN_PBE_ADDR, offsetof(struct pbe, address)); > diff --git a/arch/arm64/kernel/smccc-call.S b/arch/arm64/kernel/smccc-call.S > index d62447964ed9..0ea15c1742f3 100644 > --- a/arch/arm64/kernel/smccc-call.S > +++ b/arch/arm64/kernel/smccc-call.S > @@ -43,3 +43,25 @@ SYM_FUNC_START(__arm_smccc_hvc) > SMCCC hvc > SYM_FUNC_END(__arm_smccc_hvc) > EXPORT_SYMBOL(__arm_smccc_hvc) > + > + .macro SMCCC_v1_2 instr > + .cfi_startproc > + \instr #0 > + ldr x8, [sp] > + stp x0, x1, [x8, #ARM_SMCCC_V1_2_RES_X0_OFFS] > + stp x2, x3, [x8, #ARM_SMCCC_V1_2_RES_X2_OFFS] > + stp x4, x5, [x8, #ARM_SMCCC_V1_2_RES_X4_OFFS] > + stp x6, x7, [x8, #ARM_SMCCC_V1_2_RES_X6_OFFS] > + ret > + .cfi_endproc > +.endm > + > +SYM_FUNC_START(arm_smccc_v1_2_hvc) > + SMCCC_v1_2 hvc > +SYM_FUNC_END(arm_smccc_v1_2_hvc) > +EXPORT_SYMBOL(arm_smccc_v1_2_hvc) > + > +SYM_FUNC_START(arm_smccc_v1_2_smc) > + SMCCC_v1_2 smc > +SYM_FUNC_END(arm_smccc_v1_2_smc) > +EXPORT_SYMBOL(arm_smccc_v1_2_smc) > diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h > index f860645f6512..66fd3d582c7f 100644 > --- a/include/linux/arm-smccc.h > +++ b/include/linux/arm-smccc.h > @@ -155,6 +155,56 @@ struct arm_smccc_res { > unsigned long a3; > }; > > +#ifdef CONFIG_ARM64 > +/* TODO Need to implement for ARM too */ It would be nice to have this TODO resolved. Thanks, Jens